After I/O and clock planning, the design needs to be verified to ensure that it meets the design requirements. Vivado provides two verification methods: DRCs are used to check design violations; SSN analysis is used to estimate the conversion noise level. This article will introduce DRCs, and the 16th article of this series introduces SSN analysis.
Run DRCs
DRCs can be said to be the most stringent step in pin planning. DRCs will use a set of design check items (usually called rule deck ) to check whether the current design violates this set of rules. This article will run DRCs to check I/O ports and clock logic as an example.
Open a certain stage of the design, click Tools->Report->Report DRC, or directly click Report DRC in Flow Navigator , the following window pops up:
Results name specifies the name of the window that displays DRC results; Output file can select one to save DRC results document. In Rule Decks , select the rule deck used for DRCs. A rule deck is a set of design rules. You can select multiple rule decks at the same time, and the same rule can also be included in multiple rule decks.
According to the different design stages of running DRCs (RTL design, post-synthesis design, post-implementation design), the rule deck provided by Vivado can be selected as follows:
- default: The default rule check recommended by Xilinx;
- opt_checks: rule checks related to logic optimization;
- placer_checks: rule checks related to the layout;
- router_checks: rule checks related to wiring;
- bitstream_checks: Rule checks related to bit stream generation;
- timing_checks: rule checks related to timing constraints;
- incr_eco_checks: rule checks related to the validity of incremental ECO design modification;
- eco_checks: After completing an ECO to modify the netlist, check the rules related to connectivity and layout.
After selecting the rule deck, you can modify the design rules used in Rules as needed. An example of Tcl running DRCs is as follows:
report_drc -ruledecks default -file C:/Data/DRC_rpt1.txt- 1
If you don't want to use the rule deck provided by Vivado, you can create a user-defined rule deck and add it to the Rule Decks window. This operation needs to use Tcl code to complete, an example is as follows:
create_drc_ruledeck ruledeck_1
add_drc_checks -ruledeck ruledeck_1 [get_drc_checks {SYNTH-10 SYNTH-9 SYNTH-8 SYNTH-7 SYNTH-6 SYNTH-5 SYNTH-4}]- 1
- 2
- 3
Interactive DRCs
During the I/O layout process, the Vivado IDE will run a basic check to ensure reasonable pin assignments, but only after implementation can a check in the design ensure that the final pin assignment is completely legal. During the pin layout, the interactive I/O layout routine check will report common errors. This function can be enabled or disabled through the Auto check I/O Placement check box in the Settings of the Package window or Device window :
Interactive The inspection rules for DRCs are as follows:
- Prevent the assignment of pins of high-speed transceiver GTs to noise-sensitive pins;
- Avoid I/O standards violating design rules;
- Ensure that I/O standards will not be used for I/O Banks that do not support them;
- Ensure that Bank does not have incompatible Vcc port assignments;
- Make sure that the Bank that needs the Vref port has freely available Vref pins;
- Ensure that the global clock and local clock have appropriate assignments;
- Ensure that the differential I/O ports are set on the appropriate pins;
- Ensure that output pins are not placed on pins that only support input/
Vivado turns on the interactive DRCs function by default (interactive means that the user runs related checks after every operation), Xilinx also recommends to always turn on this function.
View DRC violation information
If the violation information is found, the DRC window will open, as shown below: the
violation information is divided into 4 levels according to the severity, and the icons are displayed in different colors:
- Advisory: Provide general status and feedback during the design process;
- Warning: The constraints and settings may not be implemented as intended by the designer, and the design results have been optimized;
- Critical warning: Some user input and constraints will not be applied or the best practices will not be followed (this kind of problem must be solved, otherwise it will be upgraded to an error in the process of generating the bit stream);
- Error: Indicate the problems that make the design results unavailable and that the software cannot solve automatically without designer intervention will terminate the design process.
The content of the violation information is generally relatively long, you can click to select it to view the information more conveniently in the Violation Properties window (if the properties window is not open, select the information to open it in the right-click menu):
Details are given in the details and the solution is given. Scheme, for the designer's reference whether to modify the design. Some information will contain some blue links, click on it to cross-detect the offending objects in other windows.
Report Methodology
In versions after Vivado 2016.1, some DRC checks are combined into a new function, Report Methodology , which runs some simplified rule checks to verify the design (such as logic mapping) and follows the UltraFast design method. After opening a certain stage of design, click this function in Flow Navigator:
If there is a design violation, it will be displayed in the Methodology window, and the information viewing method is the same as DRC. The best practice is to run this function in the Elaborated Design stage, which can help designers find design problems at an early stage and save development costs.
