"Basic Architecture of ADC and DAC"----Learning Record (1)

1 digital-to-analog converter

1.1 DAC basic architecture I: DAC string and thermometer (fully coded) DAC

The origin of the string DAC has to do with Lord Kelvin, who invented it in the mid-19th century 开尔文分压器. String DACs are quite popular today, especially in applications such as digital potentiometers with typical resolutions of 6 to 8 bits. Thermometer DACs are relatively independent of code-dependent switching glitches, making them a common building block for low-distortion segmented DACs and pipelined ADCs.

1.1.1 Switch: Simple 1-bit DAC

1 位 It is reasonable to think of a transfer switch (a single-pole double-throw SPDT switch) as a DAC, as shown in the figure, which switches the output between the reference voltage and ground or between equal positive and negative reference voltages:

图片来源于《ADC和DAC的基本架构》

Σ-Δ 型 DACThis simple device is an integral component of many complex DAC structures and serves as a basic analog component in many oversampling applications . Simple switches are easily implemented using standard CMOS processes

1.1.2 Kelvin voltage divider (string DAC)

开尔文分压器或串 DACAs shown in the structure, the N-bit version of this DAC consists of 2 N power equivalent series resistors and 2 N power switches (usually CMOS). Each node of the signal chain is connected to the output. There is a switch in each room. The output is obtained from the appropriate tap by closing one of the switches

图片来源于《ADC和DAC的基本架构》

This architecture has a voltage output that is inherently monotonic. Even if the resistor is accidentally short-circuited, the output n will not be greater than the output n+1. If all resistors are equal in value, it is 线性的, but if a nonlinear DAC is desired, it can also be designed to be nonlinear on purpose. Only two switches are active during a transition, so it is a low-glitch architecture, and the switch glitches are independent of the code, so it非常适合低失真应用

String DACs 主要缺点require a large number of resistors and switches to achieve high resolution, so it is not a commonly used simple DAC architecture. It is only recently that the advent of extremely small size IC features has made low and medium resolution DACs feasible. Simple digital potentiometer, as shown:

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Either pin of the potentiometer is 不可能处于5V 或 3V 逻辑电源以外的电位, but some potentiometers have more complex decoders, level shifters, and additional high-voltage power supply pins. Although the logic control level is very low (3V or 5V), the potentiometer pins Has a much larger voltage range, possibly up to ±15V in some cases

1.1.3 Current output thermometer (fully decoded) DAC

There is a current output DAC that is similar to a string DAC in that it 2的N次方–1 consists of switchable current sources (which can be resistors and voltage references, or active current sources) connected to an output pin that must At or near ground potential. This architecture is often referred to as “温度计”或“完全解码”DAC, as shown in the figure, it generates current through a resistor connected to a reference voltage

图片来源于《ADC和DAC的基本架构》

If an active current source is used, as shown in the figure below, the output may have greater compliance and a resistive load may be used to generate the output voltage. The load resistor must be chosen so that at maximum output current the output pin voltage remains within the rated compliance voltage range

图片来源于《ADC和DAC的基本架构》

Once the current in the thermometer DAC is switched into the circuit by increasing the digital code, any further increase in the digital code will no longer remove that current. Therefore, the structure itself 具单调性has nothing to do with the accuracy of the current. Again, like the Kelvin divider, only the advent of high-density IC processes will make this architecture feasible for implementing general-purpose medium-resolution DACs, although a slightly more complex version of it is widely used in high-speed applications, as shown :

图片来源于《ADC和DAC的基本架构》

Unlike Kelvin dividers, there is no dedicated name for this type of current-mode DAC, but both types can be called "thermometer" DACs or "fully decoded" DACs

This DAC 建立时间will still vary depending on the initial code and the final code, resulting in “码间干扰”(ISI). This problem can be solved with more complex switching techniques, where the output current returns to 0 before changing to the next value. Note that although the output current returns to 0, it is not "turned off"; when not in use, the current is discharged rather than the device being enabled or shut down.

1.2 DAC basic architecture II: binary DAC

Although string DACs and thermometer DACs are by far the simplest DAC architectures, they are by no means the most efficient when high resolution is required. 二进制加权 DACUsing one switch per bit, it is the backbone architecture of modern precision and high-speed DACs

1.2.1 Binary weighted DAC

电压模式A binary weighted resistor DAC is shown in the figure. The output impedance of this DAC changes with the input code.

图片来源于《ADC和DAC的基本架构》

电流模式Binary DAC, 基于电阻as shown on the left in the figure below, 基于电流源and as shown on the right in the figure below. This N-bit DAC consists of N weighted current sources with a ratio of N–1 power of 1:2:4:8:…:2. The current source can be composed of only a resistor and a reference voltage source. LSB Switch 2 N–1 power current, MSB Switch 1 current

图片来源于《ADC和DAC的基本架构》

1.2.2 R-2R DAC

One of the most common DAC building block structures is R-2R 梯形电阻网络as shown in the figure. It uses only two resistors of different values, with a ratio of 2:1. N-bit DAC requires 2N resistors, the adjustment is quite simple, and the number of resistors to be adjusted is relatively small

图片来源于《ADC和DAC的基本架构》

There are two ways to use an R-2R resistor ladder network as a DAC, called and “电压模式” 和 “电流模式” sometimes called "normal" mode and "inverting" mode.

电压模式 R-2R 梯形电阻 DACAs shown in the figure, the "rungs" or arms of the resistor ladder switch between VREF and ground, and the output is taken from the end of the resistor ladder. The output can be a voltage, but since the output impedance is code independent, the output can also be a current flowing into virtual ground

图片来源于《ADC和DAC的基本架构》

Advantage:

• Voltage output
• Constant output impedance, making it easier to stabilize any amplifier connected to the output node
• The switch switches the leg of the resistor ladder between the low-impedance VREF connection and ground, which is also low-impedance, so the capacitor glitch current generally does not flow to the load.

Disadvantages:

• The switch must operate over a wide voltage range (VREF to ground)
• The reference input impedance changes significantly with code, so the reference input must be driven with a very low impedance
• Gain cannot be adjusted with a resistor in series with VREF pin

电流模式 R-2R 梯形电阻 DACAs shown, the gain of the DAC can be adjusted with a series resistor on the VREF pin because in current mode, the end of the resistor ladder (with code independent impedance) acts as the VREF pin and the end of the arm is Switching between ground (sometimes an "inverting output" at ground potential) and the output line (which must remain at ground potential)

图片来源于《ADC和DAC的基本架构》

The output of the current-mode resistor ladder network is typically connected to an op amp configured as a current-to-voltage (I/V) converter, but stabilization of the op amp becomes complicated because the DAC output impedance changes with the digital code. The switch is connected directly to the output line, so its switching glitch is larger than in voltage mode. However, since the current mode resistor ladder network's switches are always at ground potential, its 设计要求较低, specifically, its voltage rating does not affect the reference voltage rating.

Among all DACs, 输出均为基准电压与数字代码的乘积, so to speak, all DACs are multiplicative DACs. But some DACs use an external reference voltage, which can vary over a wide range. These are commonly known as “乘法 DAC”或 MDACanalog outputs equal to the analog input multiplied by the digital code, and they can play an important role in many different applications.

Another common form of R-2RDAC is to switch equal currents into an R-2R network, as shown in the figure. In this architecture, the output impedance of the DAC is equal to R. This structure is often used in high-speed video DACs. A unique advantage is that regardless of resolution, only a 2:1 resistor ratio is required

图片来源于《ADC和DAC的基本架构》

The DAC shown in the figure below switches binary weighted current to the load and has a high output impedance. This architecture generally has an output compliance voltage of around 1V.

图片来源于《ADC和DAC的基本架构》

1.3 DAC basic architecture III: segmented DAC

分段 DACWhen we need to design a DAC with specific performance, it is likely that no one architecture is ideal. In this case, two or more DACs can be combined into a higher resolution DAC to achieve the desired performance. These DACs can be of the same type or different types, and the resolution of each DAC does not need to be the same

In principle, one DAC processes the MSB, another DAC processes the LSB, and their outputs are summed in some way. This process is called “分段”, and these more complex structures are called "segmented DACs"

There are two categories shown in the figure 分段电压输出DAC. The architecture of A in the figure is sometimes called a Kelvin-Varley voltage divider and consists of two or more "string DACs". There is a buffer between the first and second stages, so the second string DAC does not load the first string DAC, and the resistor values ​​in that string do not need to be the same as the resistor values ​​in the other string. However, all resistors in each string must be equal to each other, otherwise the DAC will not be linear

图片来源于《ADC和DAC的基本架构》

Instead of using the second resistor string, you can use a binary DAC to generate three LSBs, as shown in Figure B above. It is very difficult to fabricate extremely high-resolution R-2R resistor ladder networks, or more specifically, to tune them to monotonicity

无缓冲的分段串 DAC 架构as the picture shows:

图片来源于《ADC和DAC的基本架构》

The resistors in both strings must be of equal value, the only exception is that the top resistor in the MSB string must be smaller (1/2 the k power of the other resistor values), the LSB string has 2 k raised – 1 resistor, Rather than 2 to the Kth power. Since there is no buffering, this DAC 的输出阻抗随着数字代码的改变而变化

分段电流输出 DAC 结构Two examples are shown in the figure. A in the figure uses the resistor method to implement a 7-bit DAC, in which 3 MSBs are obtained through complete decoding, and 4 LSBs come from an R-2R network. B in the figure shows a similar implementation using a current source. For today's high-speed reconstruction DACs, the current source solution is currently the most popular implementation method.

图片来源于《ADC和DAC的基本架构》

The figure below shows a 6-bit DAC consisting of two fully decoded 3-bit DACs. 为使输出毛刺最小Parallel latches must be used to drive these current switches simultaneously.

图片来源于《ADC和DAC的基本架构》

1.3.1 Oversampling interpolation DAC

过采样和数字滤波Helps reduce the requirements for anti-aliasing filters in front of the ADC. Reconstructing the DAC can use oversampling and interpolation principles in a similar way

High oversampling rates move the image frequency higher, allowing the use of simpler, less expensive filters with wider transition bands. Σ-Δ 型 DAC 架构使用高得多的过采样速率, extending this principle to the extreme

过采样和插值原理也可用于通信领域的高速 DAC, in order to reduce the requirements on the output filter and use the processing gain to improve SNR

1.3.2 Reconstruct the output spectrum of DAC

The output of the reconstructed DAC can be represented as a series of rectangular pulses whose width is equal to the reciprocal of the clock rate, as shown in the figure

图片来源于《ADC和DAC的基本架构》

At the Nyquist frequency fc/2, the reconstructed signal amplitude is reduced by 3.92dB. An inverse sin(x)/x filter can be used to compensate for this effect.

1.4 Oversampling interpolation DAC

过采样/插值 DACThe basic principle is shown in the figure. N-bit input data words are received at rate fc. The digital interpolation filter operates at a clock rate equal to the oversampling frequency Kfc and inserts additional data points. At the Nyquist sampling frequency as shown in Figure A, the requirements for analog anti-image filters can be quite high. Through oversampling and interpolation, 可以大大降低对该滤波器的要求, as shown in B in the figure:

图片来源于《ADC和DAC的基本架构》

1.4.1 S-D 型DAC

Σ-Δ 型 DAC 的工作原理与Σ-Δ 型 ADC 非常相似, but in the Σ-Δ DAC, the noise shaping function is implemented using a digital modulator instead of an analog modulator. Different from the Σ-Δ ADC, the Σ-Δ DAC is mostly digital. As shown in Figure A below, it consists of an "interpolation filter", a Σ-Δ modulator and a 1-bit DAC. The output of the DAC Switch between equal positive and negative reference voltages. The output is filtered in an external analog low-pass filter (LPF), which is much less complex than at conventional Nyquist sampling rates due to the high oversampling frequency.

图片来源于《ADC和DAC的基本架构》

Σ-Δ 型 DAC 可以使用多位, the "multi-bit" architecture shown in Figure B above, its principle is similar to the interpolation DAC discussed previously, but a Σ-Δ digital modulator is added

1.5 Intentionally non-linear DAC

1.5.1 Telecom applications of nonlinear DACs and ADCs

非线性数据转换器One of the earliest uses was to digitize voice band signals for pulse code modulation (PCM) systems. The motivation for using non-linear ADCs and DACs is to reduce the total number of bits required to digitize the speech channel 从而降低串行传输速率. The non-linear 6-bit segmented DAC is shown in the figure:

图片来源于《ADC和DAC的基本架构》

The first 3 bits in the diagram determine one of 8 possible chords, and each chord is further subdivided into 8 equal levels based on the definition of 3 LSB. The 3 MSB is generated using a non-linear string DAC, while the 3 LSB is generated using a 3-bit binary R-2R DAC. The nonlinear transfer function of the 8-bit DAC is first divided into 16 segments (chords) with different slopes, specifically 斜率取决于所需的非线性传递函数. The 4 MSB determines the segment containing the required data point, and each segment is further subdivided into 16 equal quantization levels by the 4 LSB of the 8-bit word

Universal non-linear DAC, as shown in the figure:

图片来源于《ADC和DAC的基本架构》

Input data expanded with μ-law or A-law compression is mapped to data points on a high-resolution DAC transfer function. This mapping can be easily accomplished with a simple lookup table in hardware, software, or firmware. A similar nonlinear ADC can be built by using a high-resolution ADC to digitize the analog input signal and then using an appropriate transfer function to map the data points to shorter words. A huge advantage of this approach is that it eliminates the need to approximate the transfer curve with straight line segments as in the previous approach, thus providing greater accuracy

1.6 Basic principles of DAC interface

1.6.1 DAC reference voltage

Analog output 取决于是否存在称为基准电压源的模拟输入, and the accuracy of the reference is almost always the limiting factor in the absolute accuracy of the DAC

A variety of ADCs and DACs support the use of external reference voltage sources instead of internal reference voltage sources in various ways. Common configurations are shown in the figure:

图片来源于《ADC和DAC的基本架构》

• A shown in the figure is required 外部基准电压源的转换器. It is usually recommended to add a suitable decoupling capacitor near the ADC/DAC REFIN pin.
• As shown in B in the figure 内置基准电压源的转换器, the reference voltage source is also led to a certain pin on the device, and a capacitor is placed near the converter pin.
• As shown in C in the figure 采用内部基准电压源但需要额外封装引脚的转换器, REF OUT only needs to be externally connected to REF IN and decoupled as needed.
• As shown in D in the figure 采用外部基准电压源但需要额外封装引脚的转换器, REF OUT remains floating, and the external reference voltage source is decoupled and applied to the REF IN pin.
• As shown in Figure E 使用单个封装引脚以外部基准电压源来覆盖驱动内部基准电压源的配置, the value of resistor R is typically several kΩ, thus allowing the internal reference to be overridden by connecting a low-impedance external reference to the REFOUT/IN pin.
• F shown in the figure is如何连接外部基准电压源来覆盖内部基准电压源

1.6.2 DAC analog output considerations

The analog output of a DAC may be a voltage or a current, in both cases the output impedance may need to be known. If the voltage output is buffered, the output impedance will be low. Current outputs and unbuffered voltage outputs will have higher impedance and may also have reactive components as well as purely resistive components.

理论上，电流输出应当连接到电阻为零欧姆的地电位。在实际应用中，该输出将采用非零阻抗和电压

Theoretically, the current output should be connected to ground potential with a resistance of zero ohms. In a real application, this output would have non-zero impedance and voltage. Modern current output DACs typically have several differential outputs to achieve high common-mode rejection and reduce even-order distortion products. Common full-scale output voltages range from 2mA to 30mA.

In many applications, it is necessary to convert the differential output of a DAC into a single-ended signal suitable for driving a coaxial line. As long as low frequency response is not required, this can easily be achieved with an RF transformer, as shown in the figure as a typical example of this approach:

图片来源于《ADC和DAC的基本架构》

The high-impedance current output of the DAC is differentially terminated with a 50Ω resistor, thus defining the source impedance of the transformer as 50Ω. The resulting differential voltage drives the primary winding of a 1:1 RF transformer, producing a single-ended voltage at the output of the secondary winding. The output of the 50Ω LC filter is matched to the 50Ω load resistor RL, ultimately producing an output voltage of 1Vp-p. The transformer not only converts the differential output to a single-ended signal, but also isolates the DAC's output from the reactive load of the LC filter, thereby improving overall distortion performance.

When frequency response down to DC is required, 可以连接运算放大器作为差分转单端转换器来获取单端输出the AD8055 op amp as shown is used to achieve high bandwidth and low distortion

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The AD8055 is configured for a gain of 2 to ultimately produce a single-ended output voltage of 2Vp-p referenced to ground. Note that since the output signal swings above/below ground, a dual supply op amp is required

1.6.3 Single-ended current to voltage conversion

Single-ended current-to-voltage conversions can be easily performed by using a single op amp as the I/V converter. As shown, the AD768's 10mA full-scale DAC current output can produce an output voltage of 0 to +2V across a 200Ω RF resistor.

图片来源于《ADC和DAC的基本架构》

By driving the virtual ground of the AD8055 op amp,可以最大程度地减少因 DAC 输出阻抗中的非线性而导致的任何失真

1.6.4 Differential current to differential voltage conversion

If a buffered differential voltage output from a current output DAC is required, the AD813x family of differential amplifiers can be used as shown:

图片来源于《ADC和DAC的基本架构》

The DAC output current first flows through a 25Ω resistor and is converted into a voltage. Next, use the AD8138 to amplify the voltage 5 times. This technique is used instead of direct I/V conversion to prevent high slew rate DAC currents from overloading the amplifier and introducing distortion.必须小心地处理使 DAC 输出电压位于其顺从电压额定值范围之内

1.6.5 DAC data input considerations

The earliest single-chip DACs contained almost no logic circuitry, and digital inputs had to maintain parallel data to maintain digital outputs. Today, almost all DACs are latched and data is simply written to them rather than maintained. Some devices even have non-volatile latches and remember settings when powered off. “双缓冲”DAC具有两组锁存器，数据最初锁存在第一级中，然后传输到第二级,as the picture shows:

图片来源于《ADC和DAC的基本架构》

If the DAC does not have a latch or has one, all the bits must be loaded simultaneously in parallel, otherwise its output during loading may be completely different from its actual content or target content

Double buffered DAC advantages:

• The DAC is double-buffered 可以加载并行数据、串行数据、4 位或 8 位字或任何其它内容and the output is not affected until the new data load is complete and the DAC receives an update command
• By driving all switches in parallel and updating a single latch at the DAC output data rate, glitches can 最大程度地减少各个开关之间的时间偏斜be minimized and distortion performance improved
• 可以同步更新多个 DAC. Data is loaded into the first stage of each DAC in turn, and when everything is ready, the output buffers of all DACs are updated simultaneously

1.7 Basic principles of direct digital synthesis (DDS)

1.7.1 Basic principles of DDS architecture

直接数字频率合成系统的基本原理As shown, this simplified model uses a stable clock to drive a programmable read-only memory (PROM) that stores a sine wave (or other arbitrary waveform) for one or more integer cycles. As the address counter steps through each memory location, the digital amplitude of the signal corresponding to each location drives the DAC, which produces an analog output signal. The spectral purity of the final analog output signal mainly depends on the DAC

图片来源于《ADC和DAC的基本架构》

The actual DDS system uses a more flexible and effective way to achieve this function, that is, using digital hardware called a numerically controlled oscillator (NCO), as shown in the figure:

图片来源于《ADC和DAC的基本架构》

The heart of the system is the phase accumulator, whose contents are updated every clock cycle. Each time the phase accumulator is updated, the number M stored in the Δ phase register is accumulated to the number in the phase register. Practical DDS systems first need to perform a serial or byte load sequence to load the new frequency word into the internal buffer register and then load the M register.加载 Δ 相位缓冲寄存器所需的时钟周期数决定了输出频率的最大改变速率

1.7.2 Aliasing in DDS systems

An important output frequency range limitation may arise in simple DDS systems. 奈奎斯特准则表明, the clock frequency (sampling rate) must be at least twice the output frequency. The actual maximum output frequency is limited to approximately 1/3 of the clock frequency. As shown in the figure is the DAC output in the DDS system, where the output frequency is 30MHz and the clock frequency is 100MHz.

图片来源于《ADC和DAC的基本架构》

After reconstructing the DAC 必须跟随一个抗混叠滤波器to eliminate lower image frequencies (100–30=70MHz)

1.7.3 DDS system used as ADC clock driver

DDS systems (such as the AD9850) can provide an excellent method of generating the ADC sampling clock, especially suitable for situations where the ADC sampling frequency must be controlled by software and locked to the system clock, as shown in the figure using a DDS system as an ADC clock driver:

图片来源于《ADC和DAC的基本架构》

The DAC output current IOUT drives a 200Ω, 42MHz low-pass filter. The source and load impedances are terminated and the equivalent load is 100Ω. The filter can eliminate spurious frequency components above 42MHz. The filtered output drives one input of the AD9850's internal comparator. The DAC compensated output current can drive a 100Ω load. A 100kΩ resistor divider output is decoupled between the two outputs to generate a reference voltage for use by the internal comparator

1.7.4 Amplitude modulation in DDS systems

Amplitude modulation in a DDS system can be achieved by placing a digital multiplier between the lookup table and the DAC input, as shown:

图片来源于《ADC和DAC的基本架构》

Another way to modulate the amplitude of the DAC output is to change the DAC's reference voltage. In the AD9850, the internal reference control amplifier has a bandwidth of approximately 1MHz. This method is very effective when the output amplitude changes are relatively small, as long as the output signal does not exceed the +1V specification.

1.8 Digital potentiometer

The basic schematic diagram of a digital potentiometer is shown in the figure. In a normal string DAC configuration, terminals A and B are connected between the reference voltage, and the W (wiper) terminal is the DAC output. There is also an additional R resistor in the string DAC configuration to connect the A terminal to the reference voltage.

图片来源于《ADC和DAC的基本架构》

The resistor string represents the end-to-end potentiometer resistance, and the traditional "DAC output" becomes the digital potentiometer's wiper. The number of resistors in the resistor string determines the potentiometer's resolution or "step size," which currently ranges from 32 (5 bits) to 1024 (10 bits), the switch is a CMOS transmission gate that minimizes the on-resistance change between any given step and the output. The voltage on terminals A and B can be any value, as long as It can be between the power supply voltage VDD and VSS

1.8.1 Modern digital potentiometers in small packages

Shown below are three digital potentiometers in small packages:

图片来源于《ADC和DAC的基本架构》

The AD5245 shown in A in the figure adopts an 8-pin SOT-23 package and has 256 bits (ie 8 bits). The operating supply voltage range is +2.7V to +5.5V, and the maximum supply current is 8µA, while内置一个命令位，用于关断器件，使其进入零功耗状态

The AD5247 shown in B in the figure is similar to the AD5245, except that it has 128 positions (7 bits), the B end is connected to ground, and it uses an SC706 pin package. AD5247 does not have A0 function

The AD5246 shown in C in the figure is similar to the AD5245, except that it is connected with a variable resistor, and its W and B terminals are available for external use.

1.8.2 Digital potentiometer with built-in non-volatile memory

Digital potentiometers (such as the AD5245, AD5246, and AD5247) are primarily used in active control applications because they have no non-volatile memory and the settings are lost if power is removed. Most volatile digital potentiometers have a power-on preset function that forces the device to enter the intermediate level code when powered on
AD5235 是一款双通道 10 位数字电位计，以片内 E2MEM 存储目标设置. The functional block diagram is as shown in the figure:

图片来源于《ADC和DAC的基本架构》

The AD5235 allows for a variety of programming through a standard serial interface, 支持16 种工作模式和调整模式including scratchpad programming, memory storage and retrieval, increment/decrement, logarithmic tap adjustment, wiper setting readback, and user-defined additional E2MEM

1.8.3 One-Time Programmable (OTP) Digital Potentiometer

AD5172/AD5173 双通道 256 位、一次性可编程(OTP)数字电位计uses fuse connection technology to maintain the function of resistor settings in memory. The functional block diagram is shown in the figure.

图片来源于《ADC和DAC的基本架构》

I2C 兼容数字控制来编程The AD5172/ AD5173 offer an unlimited number of adjustments before permanently setting the resistor value via a 2-wire , support programmable presets and offer the advantages of excellent temperature stability and small size.非常适合其他通用数字电位计应用

AD5170 is a model 可二次编程的 8 位数字电位计, the functional block diagram is shown in the figure:

图片来源于《ADC和DAC的基本架构》

1.8.4 Digital potentiometer with 1% accuracy

The AD5291/AD5292 are single-channel, 256/1024-bit digital potentiometers with an end-to-end resistance tolerance error of less than 1% and support both 有 20 次可编程存储器±10.5V to ±15V dual power supplies and +21V to +30V single power supplies. Cursor settings can be controlled via the SPI digital interface.将电阻值编程写入 20 次可编程存储器之前，可进行无限次调整

1.8.5 AC Considerations for Digital Potentiometers

Digital potentiometers can be used in AC applications, but require 考虑内部电容产生的带宽限制问题. The figure shows an AC model of a digital potentiometer, in which the capacitances are represented by CA, CB and CW respectively.

图片来源于《ADC和DAC的基本架构》

数字电位计的带宽取决于配置，受可变电阻影响，它同时具有动态性

1.8.6 Application examples

Like op amps, digital potentiometers are building blocks in many circuits. Because digital potentiometers operate in digital control mode, they can be used in active control applications in addition to basic adjustment or calibration applications. As shown in the figure 数字电位计的两种电路应用:

图片来源于《ADC和DAC的基本架构》

The digital potentiometer shown in A in the figure is used in a programmable power supply, as shown in Figure B, where a once-programmable digital potentiometer is used to calibrate the DC bias point of the RF power amplifier, and the calibration is programmed with factory software. No need to use any external controller. Similarly, electronic equipment manufacturers use digital potentiometers in power supplies to adjust the supply voltage to cover all supply voltage conditions during reliability testing.

1.8.7 Summary

Digital potentiometers have many significant advantages over mechanical potentiometers and trimmers and are therefore widely used in modern systems

• General applications: sensor calibration, system gain and offset adjustment, programmable gain amplifier, programmable filter, programmable reference setting, traditional digital-to-analog converter, voltage-to-current converter, line impedance matching
• Computer and network equipment: programmable power supply, power trimming, battery charger given value setting, temperature control given value setting
• LCD display: backlight, contrast and brightness adjustment; LCD panel common mode voltage adjustment; programmable gamma correction; LCD projector reference voltage generator
• Consumer electronics applications: PDA backlight adjustment, electronic volume control
• RF Communications: RF power amplifier bias, DDS/PLL amplitude adjustment, VCXO frequency tuning, varactor bias, log amplifier slope and intercept adjustment, quadrature demodulator gain and phase adjustment, RFID reader calibration
• Automotive electronics: engine control device given value setting, sensor calibration, actuator control, instrument control, navigation/entertainment display adjustment
• Industrial and Instrumentation: System Calibration, Floating Reference DAC, Programmable 4 to 20mA Current Transmitter
• Optical communication: laser bias current adjustment, laser modulation current adjustment, optical receiver signal conditioning, optical attenuator, wavelength controller

致谢ADI智库出品《ADC和DAC的基本架构》

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