verilog learning (10) writing code encountered errors

I encountered a lot of bugs during the learning of verilog, and I just remembered to take notes now, alas, why did I forget it. .

1: Chapter 7 exercises, instantiating a submodule in the top-level file, vcs reports an error, saying that the submodule is not defined, after looking for a long time, I found that the submodule lacks endmodule

　　

2: include "filename.inc"; the filename.inc here must be placed in the simulation file, that is, in the same layer as the makefile, not in the same level directory where the filename.inc file needs to be included.