Developer sharing｜Execute MicroBlaze application through PSU DDR in Vitis

MicroBlaze™ CPUs are a family of modifiable drag-and-drop preset 32-bit/64-bit RISC microprocessor configurations.

MicroBlaze processors address the diverse needs of many diverse applications benefiting the industrial, medical, automotive, consumer and communications markets. MicroBlaze uses the Harvard architecture, which typically contains dual LMB BRAMs within the PL. But in this blog post, we will discuss how to execute MicroBlaze application through PSU DDR on Zynq UltraScale ZCU104 development board.
Upon exiting reset, the MicroBlaze will fetch its instructions from the memory addresses specified within the C_BASE_VECTORS parameter in the MicroBlaze configuration. In this example, this C_BASE_VECTORS will be set to a region within the PSU DDR.
However, depending on the boot process used, this can lead to potential problems where the PSU DDR may not be configured before the PL. This may cause MicroBlaze to hang. To avoid this we can use the "Reset Mode" signal on the MicroBlaze.

In the table above, you can see various reset_mode configurations. The best configuration for our use case is "01", where the MicroBlaze will remain in reset until we are ready. We will use GPIO on the PSU to de-reset the MicroBlaze via EMIO.

 

Create hardware:

 

The Vivado IP integrator block design is as follows: