Vitis Guide | Xilinx Vitis Series (5)
Hello heroes, welcome to the "Gen Linzi" column. This is the first time for Gen Linzi to meet the heroes. On the occasion of the Spring Festival, he will prepare a little gift and be disrespectful. It will bring the "Xilinx Vitis Series" to the heroes. Xia provides reference study materials, if there are any shortcomings, please give us your advice.
Due to too much content, the first article lists the catalog for heroes, and there will be time to serialize it. Today, I bring the fifth article, which introduces the use of Vitis IDE, including the establishment of the system and the Vitis IDE debugging process. Follow-up will bring detailed development tutorials, so stay tuned. Without much to say, let's get to the topic.
Introduction to VITIS
Author: Gen woods proofread: Lu Hui
The first article put a hyperlink https://zhuanlan.zhihu.com/p/350466734
The second article put a hyperlink https://zhuanlan.zhihu.com/p/350471476
The third article put a hyperlink https://zhuanlan.zhihu.com/p/350474904
The fourth article put a hyperlink https://zhuanlan.zhihu.com/p/350641410
8. Use Vitis IDE
8.3 Setting up the system
When building the system, the best practice is to use the three available build targets described in Build Targets. Each build target is represented as a separate build configuration in the assistant view. Complete these build configurations in the following order:
Simulation software: Build a software simulation (sw_emu) to confirm the algorithm functions of the host program and the kernel code working together.
Simulation hardware: Build a hardware simulation (hw_emu) to compile the kernel into a hardware description language (HDL), confirm the correctness of the generated logic, and evaluate its simulation performance.
System: Perform system hardware construction (hw) to implement applications running on the target platform.
Before starting the build command, configure each build configuration to ensure that it meets your needs. Select a specific build configuration and click the "Settings" icon to open the "Build Configuration Settings" dialog box. For more information about using this dialog box, please refer to "Vitis Build Configuration Settings".
In addition to the build configuration settings, many settings that will affect your application are included in the "Hardware Features", which can be accessed through the "Vitis Hardware Features Settings" dialog box. It is best to look at each of the "Settings" dialogs discussed in Configuring Vitis IDE.
In the assistant view, various options for the build configuration are specified. You can select the build configuration and click "Build" (
) Button to start the build process. The grape core development kit is used, and the FPGA binary (.xclbin) generated in the two parts of the construction process is used for the hardware kernel to use the grape compiler v++ command, and to compile and use the program code of the host to link the g++ compiler.
After the build process is complete, the "Assistant" view will display the specific build configuration with a green check mark to indicate that it has been successfully built, as shown in the following figure. You can open any build report, such as the "compilation summary" in the hardware function or the "link summary" in the binary container. Right-click the report in the Assistant view and select "Open in Vitis Analyzer".
After the build is complete, you can now run the application in the context provided by the specific build configuration. For example, in Emulation-SW construction, the host program and FPGA binary code are used to work together with the C model, or in Emulation-HW construction, the host program and RTL kernel code can be viewed in simulation, or the application program can be run on the target computer. Platform.
To run the application from Vitis IDE, select the build configuration and click the "Run" button () to start the default run configuration. You can also right-click the build configuration and use the "Run" menu to select a specific run configuration, or edit the run configuration according to the instructions in Vitis "Run Configuration Settings".
8.3.1 Vitis IDE guidance view
After building or running a specific build configuration, the Bootstrap tab of the Console view will display a list of errors, warnings, and suggestions related to the run or build process. The guidance view will be automatically populated and displayed in a tab in the console view. You can view the guidance message to make any changes that may be required during the code or build process.
After running the hardware simulation, the "Guide" view may look like the following figure.
In order to simplify the sorting of information in the "Guide" view, Vitis IDE allows you to search and filter the "Guide" view to find specific guidance rule entries. You can collapse or expand the tree view, or even cancel the hierarchical tree representation, and visualize the simplified representation of the guiding rules. Finally, you can select what to display in the "Guide" view by enabling or disabling the display of warnings and satisfied rules, and you can also restrict specific content based on the source of the message (such as build and simulation).
By default, the Guidance view displays all guidance information for the item selected in the drop-down menu. To limit content to individual build or run steps:
-
1. Choose Window> Preferences
-
2. Select the category Guidance.
-
3. Deselect the group guidance rule check classified by item
8.3.2 Using Vivado tools from Vitis IDE
The Vitis core development kit calls the Vivado design suite to automatically run RTL synthesis and generate FPGA binary (xclbin) during the linking process. You can choose to launch the Vivado tool directly from the Vitis IDE to interact with the project to synthesize and implement FPGA binary files. The following three commands can be accessed through the Xilinx> Vivado Integration menu to support the interaction between Vitis IDE and Vivado tools:
Open the Vivado project: This will automatically open the Vivado project (.xpr) associated with the system build configuration. In order for this feature to work, you must complete the system build beforehand so that there is a Vivado project for the build.
Opening the Vivado project will launch the Vivado IDE and open the implementation design checkpoint (DCP) file to edit the project, allowing you to more directly manage the results of synthesis and implementation. You can then use the results of this work to generate FPGA binary files by using the Import Design Checkpoint command.
Import Design Checkpoint: Allows you to specify a Vivado Design Checkpoint (DCP) file to be used as the basis for system construction and FPGA binary file generation.
Import Vivado settings: You can import a configuration file (as described in the Vitis Compiler configuration file) for use in the linking process.
Using Vivado IDE in standalone mode can explore various synthesis and implementation options to further optimize the performance and area of the core. There are other options for interacting with the FPGA build process. For more information, see Managing FPGA Synthesis and Implementation Results in Vivado Tools.
8.4 Vitis IDE debugging process
Vitis IDE provides convenient debugging functions. When executing manually, setting the executable file for debugging requires many steps. When using the debugging process, Vitis IDE will automatically handle these steps.
To prepare the executable file for debugging, the build configuration must be changed to enable the application of the debug flag. Set these options in the "Project Editor" view of Vitis IDE. Two checkboxes are provided in the "Options" section for the "active" build configuration. Host debugging can enable the debugging structure in the host compilation. Kernel debugging can enable kernel debugging.
You can also enable debugging in the "Build Configuration Settings" dialog box, as shown in Vitis "Build Configuration Settings", by selecting the build configuration in the "Assistant" view, and then clicking the "Settings" button. Alternatively, you can double-click to build the configuration. The same two check boxes appear. Although host debugging can be enabled on all targets, only software emulation and hardware emulation build targets support kernel debugging.
Running a GDB session from Vitis IDE will complete all the necessary settings. It will automatically manage the environment settings for hardware or software emulation. As described in the xrt.ini File, it configures the Xilinx Runtime (XRT) to ensure debugging support while the application is running, and manages the execution of host code, kernel code, and different consoles required to debug the server.
After setting up the build configuration for debugging, clean up the build directory and rebuild the application to ensure that the project is ready to run in the GDB debugging environment.
To start a debugging session, select the build configuration in the Assistant view and click Debug (
) Button. When you start a debugging session in Vitis IDE, the perspective will switch to the "Debug" perspective, which is configured to display other windows to manage different debugging consoles and source code windows.
After starting the application, by default, the application will stop immediately at the beginning of the function body in the host code. As with any GDB graphical front end, you can now set breakpoints and inspect variables in the host code. The grape IDE can accelerate the kernel to achieve the same function in a transparent way. For more information, see Debugging applications and kernels.
This is the end of this article, and the next article will continue to be serialized, welcome heroes to pay attention!
【QQ Exchange Group】
Group number: 173560979, in the group code: FPGA technology fans.
Years of FPGA enterprise development experience, various easy-to-understand learning materials and learning methods, and a strong communication and learning atmosphere. There are currently more than 1,000 like-minded friends in the QQ group, a pure mode without advertising, which provides a pure land for technical exchanges. From beginners to industry elites, industry leaders, etc., from the military industry to civilian enterprises, from communications, image processing to artificial intelligence and other directions.
【WeChat Exchange Group】
Now the WeChat exchange group has established 08 groups, the number of which has reached thousands of people, welcome to follow the WeChat public account of "FPGA Technology Jianghu", you can get the way to join the group.
Finish
The follow-up will continue to update, bringing Vivado, ISE, Quartus II, candence and other installation related design tutorials, learning resources, project resources, good article recommendations, etc., I hope the heroes will continue to pay attention.
The rivers and lakes are huge, continue to rush, I wish the heroes all is well, goodbye by destiny!