Foreword:
At present, the ARM Cortex-A7 bare-metal development documents and videos have been upgraded twice and continuously updated to make the content richer and the explanation more detailed. The development platform used in the full text is the Huaqing Yuanjian FS-MP1A development board (STM32MP157 development board )
For the FS-MP1A development board, in addition to Cortex-A7 bare metal development, it also includes other series of tutorials, including Cortex-M4 development, FreeRTOS, Linux basic and application development, Linux system transplantation, Linux driver development , hardware design, artificial intelligence machine vision, Qt application programming, Qt comprehensive project actual combat, etc. In addition, it is planned to upgrade the documents and videos for the Linux system porting chapter and the Linux driver development chapter, so stay tuned!
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Cortex-A7 architecture and working mode
Cortex-A7 core working mode
Cortex-A7 is based on ARMv7-A architecture and has 9 working modes.
In addition to user mode, the other eight processor modes are called privileged modes (Privileged Modes). In the privileged mode, the program can access all system resources, and can switch the processor mode arbitrarily.
The processor mode can be switched through software control, and can also be switched through external interrupt or exception handling process.
Most user programs run in user mode. When the processor works in the user mode, the application program cannot access some system resources protected by the operating system, and the application program cannot directly switch the processor mode. When it is necessary to switch the processor mode, the application program can generate exception handling, and switch the processor mode during the exception handling process. This architecture allows the operating system to control the use of overall system resources.
When an abnormal interrupt occurs in the application program, the processor enters the corresponding exception mode. In each exception mode, there is a set of special-purpose registers for the corresponding exception handler, so that the registers in the user mode (save the program running state) will not be destroyed when entering the exception mode.
Register Organization
Cortex-A7 processor register organization overview
The Cortex-A7 processor has a total of 9 different processor modes, and each processor mode has a set of corresponding register sets, as shown in the figure below, which lists the register organization and mode relationship summary of the Cortex-A7 processor .
1. In the diagram of register organization, each small square is a register, and each register is 32 bits.
2. The register has no address, and the access register is accessed by number, r0-r15, cpsr, spsr.
3. Registers of banked type are private registers, while registers of non-banked type are public registers.
4. User mode and system mode can access up to 17 registers, HYP mode can access up to 19 registers, and other modes can access up to 18 registers.
5. There are only 43 registers in the register organization, with a total of 172 bytes. Therefore, try not to define register-type variables during development. The reason is that the number of registers is limited, and register-type variables cannot be used to fetch addresses because there are no registers. address.
6. The mode of the current processor determines which set of registers can be operated, and any mode can access the following registers.
1) Corresponding R0~R12, corresponding R13 (Stack Pointer, SP, stack pointer) and R14 (the Link Register, LR, link register).
2) Corresponding R15 (PC), corresponding CPSR. Privileged mode (except System mode) can also access the corresponding SPSR. Only HYP mode can access ELR_hyp.
7. General-purpose registers can be divided into the following two categories according to whether they are grouped or not:
1) Unbanked Register, including R0~R7. Corresponding to the Low Registers in the figure below.
2) Banked Register, including R8~R12. Corresponding to the High Register in the figure below.
Ungrouped registers include R0-R7. As the name implies, in all processor modes, for each ungrouped register, it refers to the same physical register. Ungrouped registers are not used by the system for special purposes, and any application that can use general-purpose registers can use ungrouped registers. However, due to its versatility, it uses the same physical register when switching the processor mode caused by an abnormal interrupt, so it is easy to destroy the data in the register. Need to consider protection will restore.
Group registers include R8-R14, and the physical registers each of them visit depends on the current processor mode.
For group registers R8-R12, each register corresponds to two different physical registers. One set is used for all processor modes except FIQ mode, and the other set is used exclusively for FIQ mode. Such a structural design is conducive to speeding up the processing speed of FIQ. The use of registers in different modes should be distinguished by register name suffixes. For example, when using the registers in FIQ mode, registers R8 and R9 are respectively marked as R8_fiq, R9_fiq; when using the registers in user mode, registers R8 and R9 are respectively marked as R8_usr, R9_usr, etc. In the ARM architecture, R8~R12 do not have any other designated purposes, so when the FIQ interrupt arrives, there is no need to save these general-purpose registers, that is, the FIQ handler does not need to execute the save and restore interrupt scene for R8~R12
instruction, which can make the interrupt processing process very fast. So FIQ mode is often used to deal with some time-critical tasks.
R13 (Stack Pointer) Register
For group register R13, each register corresponds to 8 different physical registers. One of them is common to User mode and Sys mode, while the other 7 are used for 7 exception modes respectively. When described in the documentation, their schema is specified as needed (not required during encoding). The name form is: R13_. Among them, it can be one of the following modes: usr, svc, abt, und, irq, fiq, mon, hyp.
The R13 register is commonly used as a stack pointer in ARM processors, called SP. Of course, this is just a customary usage, and there is no mandatory use of R13 as a stack pointer, and users can use other registers as a stack pointer. In the Thumb instruction set, there are some instructions that use R13 as a stack pointer forcibly, such as stack operation instructions.
Each exception mode has its own R13. The exception handler is responsible for initializing its own R13 to point to the stack address dedicated to that exception mode. At the entry of the exception handler, the values of other registers used are saved on the stack, and when returning, these values are reloaded into the registers. With this method of protecting the program context, exceptions do not destroy the program context interrupted by it.
The address of the stack space pointed to by the stack pointer is stored in the SP stack pointer register. This stack is used to push the stack to save the scene, and it is characterized by first-in last-out.
ARM's stack belongs to the "full minus (FD)" stack, the last valid data in the SP stack, after new data is pushed into the stack, the value of SP decreases. For example, you can combine the previously imported project c_led, and add a piece of stack test code in the start.s file (if you have not touched assembly before, this process can also be done after learning assembly instructions)
Example Code 43-1 Stack Test
1 /****irq mode stack**/
2 msr cpsr,#0xd2
3 mov sp,r0
4 sub r0,#128*4
5 /*512 byte for irq mode of stack*/
6 // 加入的堆栈测试代码
7 /*******test begin*****/
8 mov r5,#0x11
9 mov r6,#0x23
10 stmfd sp!,{r5,r6}
11 ldmfd sp!,{r7,r8}
12 /*******test end*******/Add R5, R6, R7, R8, and SP to the Watch list, so that they can be updated in real time during single-step debugging.
For the convenience of observation, the data type can be adjusted to hexadecimal display
Set the breakpoint, and compare the position and content of the SP pointer before and after R5 and R6 are pushed into the stack. The figure below is the state before being pushed into the stack, the address pointed to by SP: 0xc2001f4c, the content is 0.
After R5 and R6 are pushed into the stack, the address pointed to by SP is: 0xc2001f44, and the content is 0x11. As shown below.
After SP pops two words from the stack to R7 and R8, the value of SP is restored.
(connection) register
For group register R14, each register corresponds to 7 different physical registers. One of them is common to User mode, Sys mode, and HYP mode, and the other 6 are used for the other 6 abnormal modes. When described in the documentation, their schema is specified as needed (not required during encoding). The format of the name is: R14_XXX. XXX can be one of the following patterns: usr, svc, abt, und, irp, fiq, mon.
Register R14 is also called Link Register (LR), which can be used as a general-purpose register. It has the following two special functions in the ARM architecture. Each processor mode uses its own R14 to store the return address of the current subroutine. When a subroutine is called by the BL or BLX instruction, R14 is set as the return address of the subroutine. When the subroutine returns, the value of R14 is copied to the program counter (PC). The typical approach is to use one of the following two methods.
method 1:
Execute any of the following commands.
Mov pc, lr
Bx lr
Method 2:
Use the following instruction at subroutine entry to save the PC to the stack.
stmfd sp!, {,lr}
When the subroutine returns, use the following corresponding supporting instructions to return.
ldmfd sp!, {,pc}
When an exception interrupt occurs, the specific physical register R14 of the exception mode is set as the return address of the exception mode. For some modes, the value of R14 may have a constant offset from the return address (such as data exceptions using sub pc, lr , #8 returns). The specific return method is basically the same as the above subroutine return method, but the instructions used are slightly different to ensure that the state of the program being executed is completely preserved when an exception occurs.
You can combine the previously imported project c_led and use the disassembly function to view the exit part when the sub-function is called. More specific use will be explained in the AAPCS procedure call chapter.
R15 (Program Count) Register
R15 is also called PC program count register. The PC register stores the address of the current fetch instruction (the meaning of the fetch instruction will be explained in the subsequent chapters of the pipeline). After the fetch operation is completed, the value in the PC will automatically increase by 4 to point to the next instruction.
You can still use the above test program, set the breakpoint, and the program runs to the set breakpoint "mov r5, #0x11", at this time PC=0xc20000ac, R5=0.
Add 4 to the PC address after single-step execution, R5=0x11
Program Status Register
CPSR register
The current program status register (Current Program Status Register, CPSR) can be accessed in any processor mode, it contains the following:
⚫ ALU (Arithmetic Logic Unit, Arithmetic Logic Unit) status flag backup.
⚫ Current processor mode.
⚫ Interrupt enable flag.
⚫ Set the state of the processor.
Each processor mode has a dedicated physical register as a backup program status register (Saved Program Status
Register, SPSR). When a specific abnormal interrupt occurs, this physical register is responsible for storing the contents of the current program status register.
When the exception handler returns, its contents are restored to the current program status register.
The bit assignment in the CPSR register (and the SPSR register holding it) is shown in the figure.
The definition of each status bit is given below.
8. Flag bit
N (Negative), Z (Zero), C (Carry) and V (oVerflow) are collectively referred to as condition flags. These condition flags will be modified according to the execution results of arithmetic instructions or logic instructions in the program, and these condition flags can be checked by most instructions to determine whether the instruction is executed.
In the ARM 4T architecture, all ARM instructions can be executed conditionally, but Thumb instructions cannot. The specific meaning of each condition flag is as follows.
3) N flag
This bit is set to the value of bit[31] of the running result of the current instruction. When two complement signed integers are operated, N=1 indicates that the result of the operation is negative, and N=0 indicates that the result is positive or zero.
4) Z flag
Z=1 means the result of the operation is zero
Z=0 means the result of the operation is not zero.
5) C flag bit
The setting method of C is discussed in 4 situations as follows:
⚫ In the addition instruction (including the comparison instruction CMN), when the result generates a carry, then C=1, indicating that the unsigned number operation occurs
Overflow; otherwise C=0.
⚫ In the subtraction instruction (including the comparison instruction CMP), when a misplacement occurs in the operation (that is, underflow occurs in the operation of unsigned numbers), then
C=0; otherwise C=1.
⚫ For arithmetic instructions (non-addition/subtraction instructions) that include a shift operation in the operand, C is set to the last bit shifted out by the shift register.
⚫ For other non-addition/subtraction instructions, the value of C is usually unaffected
6) V flag bit
The setting method of V is discussed below in two cases.
For addition/subtraction operation instructions, when both the operand and the operation result are signed numbers expressed in two's complement, and the operation result exceeds the range of the signed operation, it is an overflow. V=1 means sign bit overflow.
For non-addition/subtraction instructions, the value of flag bit V is usually not changed.
Although the above definitions of C and V seem quite complicated, in most cases a simple conditional test instruction is sufficient, and the programmer does not need to calculate the exact value of the condition code to obtain the desired result.
1) Q flag bit
In ARM v5 and higher with DSP instruction extensions, bit[27] is designated to indicate whether an overflow has occurred in the enhanced DAP instruction, so it is also called the Q flag. Similarly, bit[27] is also called the Q flag bit in SPSR, which is used to save and restore the Q flag bit in CPSR when an abnormal interrupt occurs. In versions prior to ARM v5 and ARM v5 non-E series processors, the Q flag is not defined and is a bit to be extended.
2) J flag bit
Supported in ARM v5 and later with Java instruction support. T=0; J=1 means in Jazelle state
9. Control bits
The lower 8 bits of CPSR (I, F, T, and M[4:0]) are collectively referred to as control bits. When an exception occurs, the value of these bits will change accordingly. In addition, if you are in privileged mode, you can also modify the value of these bits through software programming.
7) Interrupt disable bit
I=1, IRQ is disabled.
F=1, FIQ is disabled.
8) Status control bits
The T bit is a status control bit for the processor.
T=0, the processor is in ARM state (that is, executing 32-bit ARM instructions).
T=1, the processor is in Thumb state (that is, executing 16-bit Thumb instructions).
10. Mode control bit
M[4:0] are used as bit mode control bits, the combination of these bits determines which state the processor is in. The specific meanings are listed in the table.
Only the combinations listed in the table below are valid, other combinations are not valid.
Status control bits M[4:0]
11. IF-THEN flag
Bits[15:10,26:25] in CPSR are called if-then flag bits, which are used to control the if-then-else statement blocks in the thumb instruction set. The thumb language is not the focus of learning (in practical applications, the compiler basically completes the generation of the thumb), so I won’t introduce it in detail here, so everyone can understand it.
12. E control bit
Big and small endian control bit: E=1 is set to big endian mode, E=0 is little endian mode.
13. A position
A=1 disables imprecise data exception
SPSR register
spsr: Saved Program Status Register ----> Saved Program Statued Register
The spsr register is mainly used to save the cpsr register. For example, in the figure below, the application in the case of interruption.
Note: During the interrupt process, the processor automatically keeps cpsr to spsr_irq. It will be explained in detail in the exception handling chapter later.
It can be combined with the previously imported project c_led. In the start.s file, when the stack is initialized, it will enter each mode and set the stack address. It can be seen that after the msr instruction (which will be introduced in the subsequent assembly instruction chapter), the M[4:0] of cpsr will change, and then the system enters the corresponding mode.
