Linux Bare Metal Development Series 7 Based on IMX6ULLmini: Interrupt Processing Process

interrupt context

The cpu runs instructions and reads and writes data through the kernel registers. Its specific value at the moment before entering the interrupt is called the interrupt context.

Interrupt context refers to the register state and other related information saved by the CPU before entering the interrupt. When the CPU receives an interrupt request, it saves the state of the currently executing instruction and switches the value of the register to a specific context in order to handle the interrupt. (Protect the scene)

The interrupt context includes the value of the CPU registers, the value of the program counter (PC), the value of the stack pointer (SP), and other status information related to interrupt processing. This information is kept in a specific location in memory, usually called the interrupt vector table or interrupt descriptor table.

When the interrupt handler is completed, the CPU will restore the previous register state from the interrupt context, and continue to execute the interrupted program or task. This context switching process is called the interrupt handling process

specific process

• Initialize the stack pointer in IRQ mode: Before entering the interrupt, you need to allocate a stack space for IRQ mode and initialize the stack pointer to this space.

• Enter IRQ mode: The CPU switches to IRQ mode to execute the interrupt handler.

• CPSR register: Save the value of the CPSR register in the current running state so that it can be restored after the interrupt processing is completed.

• Save Context: Save the context of the currently executing instruction to the stack. This includes saving general purpose registers, saving LR (link register, saving return address), saving SPSR (saving current program state register), etc.

• Get Interrupt Number: Read the value in the relevant register of the interrupt controller (GIC) to get the number that triggered the interrupt.

• Read GIC base address and GICC base address: Get the base address of GIC (Interrupt Controller) and the base address of GICC (GIC CPU Interface) from the system configuration.

• GICC_IAR Register: Read the GICC_IAR register, which holds the number of the highest priority interrupt.

• Execute the interrupt processing function: According to the interrupt number, find the corresponding interrupt processing function in the IRQ interrupt service table, and execute the function.

• Restore context: restore previously saved context information from the stack, including restoring general-purpose registers, restoring LR, restoring SPSR, etc.

• Return to the original program: According to the previously saved return address, return from the interrupt handler to the original interrupted program to continue execution.

cpsr register

• bit31: Negative number flag bit

• bit30: Zero flag bit

• ...

• M[4:0]: Operation mode control bits

  • 10000: User mode

  • 10001: FIQ mode

  • 10010: IRQ mode

  • 10011: SVC mode

  • 10111: Abort mode

  • 11011: Undef mode

  • 11111: System mode

  • 10110: Monitor mode

  • 11010: Hyp mode

mrs <Rt>,cpsr //Read cpsr 
msr cpsr,<Rt> //Write cpsr 
cps #xx //Write immediate data to M[4:0] in cpsr

GICC base address

4.1.3 CPU interface register ma (GIC official manual)

Three-stage pipeline

• Fetch instructions (pc)

• translation instruction

• execute command

• 

lr = pc = current execution instruction + 8 
The next one of the current execution instruction: lr-4

arm:PC=current execution instruction address+8_armpc+8_aoXiaMi's Blog-CSDN Blog

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