Linux bare-metal development series five based on IMX6ULLmini: General Interrupt Controller (GIC)

Table of contents

GIC structure

Get GIC interrupt controller base address

Method 1: Query the chip data sheet

Method 2: Query the cp15 coprocessor

CBAR register

SCTLR register

VBAR register

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GIC is used to manage interrupt resources in single-core or multi-core chips

• ARM has developed 4 versions of the GIC specification, V1~V4

• ARMv7-A core is used with GIC-400

GIC structure

GIC Official Manual: ARM® Generic Interrupt Controller

• V2 supports up to 8 cores

• Three types of signal sources:

  • Software interrupt: for multi-core communication, ID0~ID15

  • Private interrupt: kernel unique interrupt, ID16~ID31

  • Shared interrupt: interrupt shared by all cores, ID32~ID1019

• Distributor: Select which CPU interface unit to send the interrupt signal to

  What are the associated registers?

  • Number of interrupts: GICD_TYPER

  • Interrupt Clear: GICD_ ICENABLERn

  • Interrupt enable: GICD_ISACTIVERn

  • Interrupt priority setting: GICD_IPRIORITYR

• cpu interface unit: After processing the signal, send the signal to the CPU

  What are the associated registers?

  • Number of interrupt priorities: GICC_PMR

  • Preemption priority and sub-priority settings: GICC_BPR

  • Save Interrupt ID: GICC_IAR

  • Notify cpu interrupt completion: GICC_EOIR

Get GIC interrupt controller base address

Method 1: Query the chip data sheet

 

Method 2: Query the cp15 coprocessor

There are 16 in total: c0~c15. Each coprocessor itself has multiple meanings and needs to be configured step by step

//Set and read coprocessor
 MRC {cond} p15, <opc1>, <Rn>, <CRn>, <CRm>, <opc2> 
//Set and write coprocessor MCR {cond} p15, <opc1> , <Rn>, <CRn>, <CRm>, <opc2>

• cond: execution condition, generally omitted

• opc1: first layer settings

• Rn: general purpose register

• CRn: the coprocessor to set

• CRm: Second Layer Settings

• opc2: Layer 3 settings

B3.17 Oranization of the CP15 registers in a VMSA implementation

CBAR register

CRn=c15，opc1=4，CRm=c0，opc2=0

• Address of GIC

MRC p15, 4, r1, c15, c0, 0 ;获取 GIC 基地址

SCTLR register

CRn=c1，opc1=0，CRm=c0，opc2=0

 

• bit13: Interrupt vector table base address

• cache\mmu\branch prediction...

  MRC p15, 0, <Rt>, c1, c0, 0 ; Read the SCTLR register and save the data to Rt. 
  MCR p15, 0, <Rt>, c1, c0, 0 ; Write the data in Rt to the SCTLR(c1) register.

VBAR register

CRn=c12，opc1=0，CRm=c0，opc2=0

• bit5~31: Interrupt vector table offset address

MRC p15, 0, <Rt>, c12, c0, 0 ; Read the VBAR register and save the data to Rt. 
MCR p15, 0, <Rt>, c12, c0, 0 ; Write the data in Rt to the VBAR register.