In recent years, with the launch of a new generation of HDL such as Bluespec, Chisel, SpinalHDL, and PyMTL, the industry has gradually felt the improvement of the efficiency of digital chip design by the new generation of HDL. Compared with Verilog and VHDL, these new-generation HDLs have greatly improved in terms of grammatical expression ability, code succinctness, and error checking; compared with high-level comprehensive HLS, these new-generation HDLs support RTL-level description capabilities. The control aspect is far beyond HSL. The purpose of agile design of digital chips is to improve hardware design efficiency and reduce human errors. No matter which language is used for hardware design, solid hardware design-related knowledge behind it is essential, especially architecture, because architecture specializes in CPU design, and CPU is one of the most complex digital chips today . Common digital chip design issues can find corresponding references in the field of architecture, such as pipelines, caches, memory management, cache consistency, exception handling, and so on.
Although the computer science and electronic engineering majors in domestic colleges and universities have courses related to architecture or composition principles, there is a lot of content missing in the practical link, especially the parts related to cache, memory management, and exception handling in the CPU. not involving. However, as the scale of digital chips becomes larger and larger, the complexity of chip design increases exponentially, which places high demands on digital chip designers. When students who are interested in digital chip design move from school to society, how to understand the essence of digital chip design and improve their design capabilities becomes the key to being competent in digital chip design.
For this reason, Datan Technology has initiated the establishment of a hardware design learning community since 2023 , and sincerely invites all students who are interested in hardware agile development and design to join our learning community. There are like-minded friends, mutual self-study groups with common learning goals, and teaching assistants who answer questions patiently. We spent a month together to systematically learn about computer architecture and verify the results of learning through hands-on projects.
learning purpose
- Cultivate digital chip designers' in-depth understanding of digital chip design, strengthen theoretical knowledge while improving practical skills, and then overall improve design capabilities;
- Cultivate digital chip design talents with both theoretical and practical capabilities
Learning Content
Based on the content and Lab practice of three MIT courses 6.004, 6.175 and 6.375. The reason for choosing these three courses is mainly because these three courses are related to elementary, intermediate, and advanced computer architecture. In particular, the Lab and course projects of 6.175 and 6.375 have a certain degree of difficulty, requiring the use of Bluespec language to implement RISC-V processors, and support functions such as multi-level pipeline, branch prediction, cache, exception handling, and cache consistency. In addition, the Lab link also involves the joint development of software and hardware, requiring the real RISC-V program to be run based on the implemented RISC-V processor, and a performance evaluation is given.
Therefore, Datan Technology chooses these three courses as the learning content, in order to help students who are interested in digital chip design strengthen the basic knowledge of architecture , improve digital chip design capabilities, and lay a solid foundation for future digital chip design positions.
Basic entry:
【MIT 6.004】https://b23.tv/o7YjSkA
Advanced upgrade:
[MIT 6.175] A total of 23 lectures, 8 labs, and 1 project
【MIT 6.375】A total of 13 lectures, 5 labs, and 1 project
Assessment:
The assessment of this learning community self-study course is based on the completion of Lab practice as the standard, and all Labs and projects are required to realize the established functions and pass the simulation verification.
suitable for the crowd
- Have a certain HDL language foundation, such as Verilog, VHDL, SystemVerilog, etc.;
- Have strong self-learning ability;
- One month of full-time study is required.
learning method
- Mainly self-study, everyone in the community supervises and communicates with each other, and the community provides teaching assistants to answer questions online;
- Provide expert comments and guidance upon completion of the project.
study plan
- MIT 6.004 (Students with basic knowledge can skip it): Normally it takes 1-2 days and does not involve Lab practice;
- The first half of MIT6.175+6.375: It takes about 2 weeks to learn the first 8 Lectures of 6.175 and the first 9 Lectures of 6.375, and complete the first 4 Labs of 6.175 and the first 4 Labs of 6.375;
- The second half of MIT6.175+6.375 : the overall difficulty is upgraded, it will take about 3 weeks to learn the remaining content of 6.175 and 6.375, and complete the last 4 Labs of 6.175, the course project of 6.175 and the fifth Lab of 6.375;
- Submit the code to GitHub after the Lab and project are completed for review;
- If you have any questions during the process, you can ask the teaching assistants in the group at any time.
way of participation
- Prepare your personal resume, including but not limited to: school/professional, past academic/project experience
- Scan the QR code to contact the little assistant to sign up, register the learning files, and join the hardware design learning community group after passing to participate successfully.