Overview of Embedded Hardware System (SOPC) for FPGA Learning (Software and Hardware Design)
First of all, we know that FPGAs can implement logic that acts as a complete microprocessor and provide many flexibility options. The figure below shows why FPGA devices are field programmable gate array devices.
In order to make the FPGA-based embedded system be able to act as a microprocessor system, then we must learn the NIOS II (SOPC) system design, and the system should include the following content when designing, because the microprocessor and FPGA The difference is that the FPGA does not contain any logic when it is powered on (due to the SDRAM process), and we need to configure the FPGA processor before the system runs.
(1) JTAG interface supports FPGA configuration and hardware and software debugging
(2) Power-on FPGA configuration mechanism
So what is an FPGA embedded system?
Simply put, one or more CPUs are placed inside the FPGA device.
FPGA itself is hardware processing, and the CPU placed inside the FPGA needs software processing, so that the established system can coordinate the connection between software and hardware.
And such a system can be tailored.
So what is the difference between SOPC and SOC? What does P stand for?
One word difference is actually two different modes, and the flexibility of this programmability "P" has the following two aspects:
(1) The CPU itself can be modified
- CPU scale: three modes, economy type, standard type and fast type.
- Frequency: 50MHz by default, can be increased or decreased
- MMU------Yes/No
- Cache-------iCache instruction cache, dCache data cache
- instruction. Complicated data processing is completed with one instruction, which can accelerate
(2) Customize the peripherals of the bus
But in today's development, the ARM series programming seems to be more popular, and the NIOS II system seems to be eliminated in actual industrial applications.
The figure below is the general design flow of the NIOS II system
From the process shown in the above figure, it can be seen that the definition and generation of the system in the platform includes two aspects: one is the hardware design process and the software design process. Moreover, the resources required by the two processes are completely different. The hardware design requires the NIOS II core and standard components to achieve, while the software design requires single-room user instructions and peripheral equipment system software.
The following figure is the hardware design flow of the NIOS II system
It can be seen from the figure above that when designing the hardware of the NIOS II system on the platform, the NIOS II core and standard components are required. It can be seen that the standard components, that is, the IP core, are indispensable in the design of the SOPC system, and the quartus software comes with some commonly used IP cores. , The directory structure is as shown in the figure below. It can be seen that the component library contains IP cores such as PIO and Bridges, as well as user-defined user grouping IP cores. How to use the specific ip core and how to customize the ip core will be learned and recorded later.
In the above hardware design process, it is also seen that we need to perform clock constraints on the system, and this step is indispensable. Therefore, when designing the NIOS II system, we will start to enter the clock constraint unit to learn, because in the previous Verilog In a simple system implemented by grammar, clock constraints are dispensable, which is not very important. However, in the NIOS II hardware system, clock constraints are the key to the success or failure of the system and are related to the normal operation of the entire NIOS II system.
Since the NIOS II system software development process involves the C or C++ programming language, individuals are not very familiar with it, so in the later development process, only the introduction of the NIOS II system software will be involved, such as how to call the interface, the Avalon bus How to find static and dynamic addresses? It will not introduce how to design the software.