The Intel 64 and IA-32 architectures provide mechanisms for managing and improving the performance of multiple processors connected to the same system bus. These include:
• Bus locking and/or cache coherency management for performing atomic operations on system memory.
• Serialize instructions.
• An Advanced Programmable Interrupt Controller (APIC) located on the processor chip (see Chapter 10, "Advanced Programmable Interrupt Controller (APIC)"). This feature was introduced by Pentium processors.
• L2 cache (level 2, L2). For Pentium 4, Intel Xeon and P6 series processors, the L2 cache is included in the processor package and is tightly coupled to the processor. For Pentium and Intel486 processors, pins are provided to support external L2 cache.
• L3 cache (level 3, L3). For Intel Xeon processors, the L3 cache is included in the processor software package and is tightly coupled to the processor.
• Intel Hyper-Threading Technology. Extensions to the Intel 64 and IA-32 architectures enable a single processor core to execute two or more threads simultaneously (see Section 8.5, "Intel® Hyper-Threading Technology and Intel® Multi-Core Technology").
These mechanisms are particularly useful in symmetric multiprocessing (SMP) systems. However, they can also be used when an Intel 64 or IA-32 processor and a dedicated processor (such as a communications, graphics, or video processor) share the system bus.
These multiprocessing mechanisms have the following characteristics:
• Maintaining system memory coherency - when two or more processors simultaneously attempt to access the same address in system memory, some communication mechanism or memory access protocol must be used to improve data coherency, and in some cases allow a The processor temporarily locks a memory location.
• Maintain cache coherency - When one processor accesses data cached by another processor, it cannot receive erroneous data. If data is modified, all other processors accessing that data must receive the modified data.
• Allows predictable order of writes to memory - In some cases it is important to observe memory writes externally in the same order as programmed.
• Distribute interrupt handling among a set of processors - When multiple processors are running in parallel in a system, it is useful to have a centralized mechanism to receive interrupts and distribute them to the available processors for processing. Improve system performance by taking advantage of the multi-threaded and multi-process nature of contemporary operating systems and applications.
Cache mechanisms and cache coherence for Intel 64 and IA-32 processors are discussed in Chapter 11. Chapter 10 will introduce the APIC architecture. Bus and memory locking, serialized instructions, memory ordering, and Intel Hyper-Threading Technology are covered in the following sections