Reviewing can't get any better! ! ! !
(Quick death soon!!!)
Chapter 1 Definition of Embedded:
PCB is a general-purpose computer, and embedded system is a "special-purpose computer application system". It has the commonality of general computer composition and is also composed of hardware and software. Embedded systems generally consist of embedded microprocessors, storage and I/O parts, peripherals and execution parts, embedded software, etc.
It consists of four parts.
The basis of an embedded microprocessor
Embedded microprocessor
3. Briefly describe the design and development process of embedded system products.
Answer: ① In the development process of embedded systems, the general method is to first program in the integrated development environment on a general-purpose PC; Binary code; ③ Then through the embedded debugging system to debug correctly; ④ Finally, download the program to the target platform to run
2 main components of embedded:
The composition of the embedded system mainly consists of: embedded hardware system, embedded software system.
(1) Embedded hardware systems mainly include: embedded processors, memories, analog circuits, power supplies, interface controllers, connectors, etc.
1) Embedded processor: It is the core of the embedded system. The biggest difference between embedded processors and general-purpose processors is that most embedded CPUs work in systems designed for specific user groups.
2) Memory: static volatile memory (RAM, SRAM), dynamic memory (DRAM, SDRAM), non-volatile memory (ROM, EPROM, EEPROM, Flash).
3) Embedded peripheral hardware devices: serial port, Ethernet interface, USB, audio interface, LCD display, camera, etc.
(2) Embedded software systems mainly include: underlying drivers, operating systems, and applications
1) Bottom driver: realize the interface between embedded system hardware and software.
2) Operating system: OS for short. Realize the process scheduling and task processing of the system. The core of the operating system is the embedded processor.
3) Application program: the application that realizes the system function.
3 Classification of Embedded Systems:
One: Harvard body structure: Harvard structure data space and address space are separated.
1. Von Neumann architecture: The most notable feature of Von Neumann (VON-NEUMANN) type computers is that instructions and data share memory, instruction bus and data bus share. Instruction fetch and data fetch are done through the same bus. The CPU cannot fetch instructions and fetch data at the same time.
Difference : The main difference between the two is whether the data space and the program space are separated. The editing method of the address space is different. Haval is a data bus, and the instruction addresses are separated. They are traversed separately and accessed independently, thereby improving the operating speed of the processor (CPU). It is convenient to take the address and take the data.
In the ARM processor series, ARM7 adopts the VON NEUMANN architecture, while ARM9 and above adopt the HARVARD architecture.
RISC is an acronym for Reduced Instruction Set Computer, and its goal is to design a simple and effective instruction set that can be executed in a single cycle at a high clock frequency. The ARM core adopts the RISC architecture, so it has the structural characteristics of RISC:
Has a large number of general-purpose registers;
Unique load/save (load-store) structures (ldr, str, ldm, stm);
Simple addressing modes;
Uniform and fixed-length instruction format.
Classification of embedded system kernels :
1 ARM architecture and VLSI implementation technical features Combining simple hardware and instruction sets is the basis of RISC thinking; but still retains some CISC features, and thus achieves a higher code density than pure RISC, making ARM obtain Its power efficiency and small core area. VLSI implementation technology
arm concept (four) 1 company name 2. architecture based on rise architecture 3 arm product ip core 4 arm produced device
Chapter 2 ARM Series Core
2.1 What is ARM? ARM is a company that only does CPU design and operates by selling IP. It is a semiconductor manufacturer. ARM is also an architecture, a structural system, and the latest is the ARM Cortex architecture.
ARM Architecture Features
Small size, low power consumption, low cost, high performance
Support Thumb (16-bit) and ARM (32-bit) dual instruction sets, with good compatibility.
A large number of registers are used, the execution speed is fast, and data operations are completed in registers.
A total of 37 registers with 7 different processing modes
The addressing mode is flexible and simple, the instruction length is fixed, and the execution efficiency is high.
2.2 ARM instruction set and Thumb instruction set
ARM instruction set features:
It is a typical reduced instruction set. Fixed 32-bit instruction width, the instruction structure is very regular, convenient for storage, transmission, analysis and execution. The Thumb instruction set has been added since ARM7.
Thumb instruction set features:
The Thumb instruction set is a reduced 16-bit instruction set. It can only complete most of the functions of 32-bit standard ARM, but its 16-bit design can effectively reduce the size of the binary code, reduce the requirements for memory capacity, and reduce costs. But it makes the entire CPU more loaded, especially developers must carefully handle the switching of the two types of instruction set modes.
Corter: A : Introduction to CortexTM-A8 processor: This processor is the first application-level processor based on ARMv7 architecture developed by ARM. It is characterized by the use of technologies that can increase code density and enhance performance, and can support multimedia and NEONTM technology for signal processing capabilities, and Jazelle@RTC technology that supports ahead-of-time and just-in-time compilation of Java and other text code languages. Many advanced technologies make it suitable for various high-end application fields such as home appliances and electronics industries.
R : Introduction to CortexTM-R4 processor: This processor is the first advanced embedded processor based on ARMv7 architecture, and its main target is high-volume advanced embedded application systems, such as hard disks, inkjet printers, and automotive security systems etc.
Introduction to CortexTM-R4F processor : This processor adds error code correction (ECC) technology, floating-point unit (FPU) and aDMA integrated configuration capabilities on the basis of CortexTM-R4 processor, which enhances the memory protection of the processor. cells, caches, tightly coupled memory, DMA access, and debug capabilities.
M : Introduction to CortexTM-M3 processor: This processor is the first processor based on ARMv7-M architecture. It adopts the execution method of pure Thumb2 instructions and has extremely high computing power and interrupt response capability. Cortex-M3 is mainly used in embedded applications that are sensitive to power consumption and cost, such as automotive body systems, industrial control systems, and wireless networks. The cheapest ARM microcontroller based on this core currently sells for $1.
The second chapter corter-M3 working mode and working state :
Working mode: 1 Processing mode: exception, interrupt. There is only one code and execution permission
2-thread mode: normal execution mode. Code and execution permissions have privileged and non-privileged levels, default: privileged thread mode
Two kinds of stack pointers and registers are different FSP\PSP
Thread mode: process stack FSP\PSP
Processing Mode: Main Stack PSP
Working state: 1thumb state, normal execution state, 2 shutdown debugging state
How many registers are there in total
(1) General-purpose register group (16):
(2) Special function registers:
① Program status register group (PSRs or xPSR):
The program status register is divided into three sub-status registers (three-in-one register):
Application program PSR (APSR), interrupt number PSR (IPSR), execution PSR (EPSR)
Why is the Executive Status Register EPSR needed?
LDM, STM and If-then instructions are multi-cycle instructions. If an exception occurs during the execution of the above multi-cycle instructions, the processor will temporarily stop the operation of the above instructions and enter an exception. At this time, the site needs to be protected.
②Interrupt mask register group (PRIMASK, FAULTMASK, BASEPRI):
Used to control the enabling and disabling of exceptions, access is only allowed at the privileged level
③Control register (CONTROL):
Used for privileged mode selection and stack pointer selection
8. Cortex-M3 processor architecture
Hierarchical processor integrating core and advanced system peripherals
Cortex-M3 core: Harvard architecture, three-stage pipeline with branch prediction function, ThumbR-2 instruction set and traditional Thumb instruction set, ALU with hardware division and single-signal cycle multiplication.
Cortex-M3 processor: Cortex-M3 core, configurable interrupt controller, bus matrix, advanced debugging components Optional MPU & ETM
Thumb2 instruction set features:
Thumb2 strikes a balance between the former two, and has the advantages of both. When an operation can be completed with a 32-bit instruction, it uses a 32-bit instruction to speed up the operation, and when an operation only needs a 16-bit instruction. When a bit instruction is completed, a 16-bit instruction is used to save storage space.
The bus matrix is used to connect the processor and debug interface with the external bus. The bus matrix is connected to the following external buses:
The I-Code bus, which is used to fetch instructions and vectors from the code space, is a 32-bit AHB-Lite bus.
The D-Code bus, which is used for data load/store and debug access to the code space, is a 32-bit AHB-Lite bus.
The system bus, which is used to perform instruction fetches and vectors, data load/store, and debug access to system space, is a 32-bit AHB-Lite bus.
PPB bus (External Private Peripheral Bus), which is used for data load/store and debug access to PPB space, is a 32-bit APB (v3.0) bus.
The bus matrix also controls the following aspects : 1 unaligned access. The bus matrix converts unaligned processor accesses to aligned accesses. 2Bit-banding bit band operation. The bus matrix translates bit-band alias accesses into accesses to bit-band regions. 3 buffers. The bus matrix contains a single-entry write buffer that insulates the processor core from bus latency.
memory format little-endian high-amplification
The Cortex-M3 typically accesses code in little-endian format, which is the default memory format for ARM processors.
The area that supports bit band operations is the bit band area .
The bit band alias area serves the bit band area, and the operations on the bit band alias area will eventually be reflected on the bit band area. When we operate the bit band alias area, it is equivalent to operating the address of the bit band area.
Why use bit-band operations? One is because of fast access, and the other is because of security.
The core structure of Cortex-M3:
It is a 32-bit processor core, adopts Harvard structure, has independent instruction bus and data bus, can be accessed in parallel, and addresses are uniformly assigned and addressed. Uses a 3-stage pipeline : fetch, decode, and execute
During normal operation, one instruction is being executed while the next (second) instruction is being decoded and a third instruction is being fetched from memory.
The only way from user level to privileged level is through exceptions
Exception priority:
Software takes precedence over hardware
Preemptive priority role: interrupt nesting
Internal resource block diagram
Chapter 3 Clock System
3 low power consumption modes: 1 standby minimum 2 stop 3 sleep
Note: The general steps to set the clock: ① enable (including not bypassed) ② wait for ready ③ switch to the target clock (default is HSI)
System clock:
Briefly describe the types of STM32 clocks.
Answer: STM32 provides three different clock sources, all of which can be used to drive the system clock SYSCLK. These three clock sources are respectively
1 HSI oscillator clock: The HSI clock signal is generated by the internal 8MHz RC oscillator , which can be used as the system clock directly or as the PLL input after dividing by 2. The HSI RC oscillator can provide the system clock without any external components. Its startup time is shorter than HSE crystal oscillator. However, its clock frequency accuracy is low even after calibration .
2 HSE oscillator clock: HSE external crystal/ceramic resonator with high precision. HSE user external clock:
3 PLL clock: If you need to use the USB interface in the application, the PLL must be set to output a 48 or 72MHZ clock to provide a 48MHz USBCLK clock.
External Clock: LSE Clock The LSE crystal is a 32.768kHz low speed external crystal or ceramic resonator. It provides a low-power and accurate clock source for a real-time clock or other timing functions. The LSE crystal is enabled and disabled by the LSEON bit in the Backup Domain Control Register (RCC_BDCR).
Internal Clock: LSI Clock The LSI RC acts as a low-power clock source that can keep running in shutdown and standby modes, clocking the independent watchdog and auto- wake-up units . The LSI clock frequency is about 40kHz (between 30kHz and 60kHz). The LSI RC can be enabled or disabled by the LSION bit in the Control/Status Register (RCC_CSR).
Three resets:
1 System reset 2 Power-on reset 3 Backup area reset
Chapter 4: Naming Rules of Control Library Functions
no string variable
Chapter 5: Eight working modes of GPIO: input floating ─ input pull-up ─ input pull-down ─ analog input ─ open-drain output ─ push-pull output ─ push-pull multiplexing function ─ open-drain multiplexing function. four inputs four outputs
22. What are the GPIO configuration modes of STM32? How to configure the configuration mode? 8 types
1. GPIO_Mode_AIN analog input 2. GPIO_Mode_IN_FLOATING floating input 3. GPIO_Mode_IPD pull-down input
4.GPIO_Mode_IPU pull-up input 5.GPIO_Mode_Out_OD open-drain output 6.GPIO_Mode_Out_PP push-pull output
7. GPIO_Mode_AF_OD multiplexed open-drain output 8. GPIO_Mode_AF_PP multiplexed push-pull output
Functions of seven GPIO registers: 1 port configuration low register (GPIOx_CRL) (x=A..E). 2-port configuration high register (GPIOx_CRH) (x=A..E). 3-port input data register (GPIOx_IDR) (x=A..E). 4-port output data register (GPIOx_ODR) (x=A..E). 5 Port Bit Set/Clear Register (GPIOx_BSRR) (x=A..E). 6 Port Bit Clear Register (GPIOx_BRR) (x=A..E). 7 Port Configuration Lock Register (GPIOx_LCKR) (x=A..E)
These seven require per-sub accesses that do not allow byte-by-byte accesses
Chapter 7 Serial Port
Asynchronous serial communication data frame: four parts of the frame structure: start bit, data bit parity bit stop bit
Bit rate = baud rate × binary digits corresponding to a single modulation state
If you are using a baud rate of 9600, the bit rate of the serial port is
9600Bps×1bit = 9600bps
Send in query mode, interrupt receive
chapter eight:
Briefly describe the functional characteristics of TIM in STM32. STM32 provides advanced control timer TIM1/8, general timer TIM2~5, basic timer TIM6/7. These timers are composed of 16-bit auto-reload counters driven by a programmable prescaler. They can all do some basic timing, and can also do PWM output or input capture. In addition, the advanced control timer has brake input, complementary output and repetition counter functions, and the basic timer has the function of triggering the DAC synchronization circuit.
Types of timers: There are 11 timers in STM32, including 2 advanced control timers 18, 4 ordinary timers 2345 and 2 basic timers 67, as well as 2 watchdog timers and 1 system tick Timer SysTick. All count resolution 16 bits can generate DMA. Prescaler coefficient 1~65535. The counting type of the timer:
Basic Timer: Up Timing Only
Advanced control timer, general timer: 1 up/down timing (central alignment timer) 2 up, 3 down;
Advanced Control Timer, General-Purpose Timer: Four more channels: capture/compare channel 4
Advanced control timer: with complementary output
6. The 16-bit counter of the STM32 general-purpose timer TIM can work in three ways, namely counting up mode, counting down mode and counting up and down mode.
Calculation of timing time
1. PSC = 72-1, timer frequency = 72M/(PSC+1)=1MHZ
2. ARR = 1000-1, counting from 0 to 999, counting 1000 times
3. Interrupt period T = 1000 *1/1000000 = 1mS
5. The NVIC of STM32 manages interrupts including Cortex-M3 core exceptions. It is closely connected to the interface of the ARM processor core, which can realize delayed interrupt processing and effectively handle subsequent interrupts .
Chapter 10 Working Principle of ADC
12-bit ADC is a successive approximation analog-to-digital converter. 12 binary digits, precision and resolution. 2.4~3.6V
Operating mode: The input clock of the ADC must not exceed 14MHz
ADC main features: ● 12-bit resolution ● Interrupt on end of conversion, injection end of conversion, and analog watchdog events ● Single and continuous conversion modes ● Auto-scan mode from channel 0 to channel n ● Self-calibration ● In-band Data alignment with embedded data consistency ● Sampling interval can be programmed individually by channel ● External trigger option for both regular and injected conversions ● Burst mode ● Dual mode (devices with 2 or more ADCs) ● ADC conversion time: ─ STM32F103xx enhanced Type products: 1μs when the clock is 56MHz (1.17μs when the clock is 72MHz) ● ADC power supply requirements: 2.4V to 3.6V ● ADC input range: VREF- ≤ VIN ≤ VREF+ ● DMA requests are generated during regular channel conversion.
There are 16 multiplex channels. Transformations can be organized into two groups: rule groups and injection groups. A series of conversions in any order on any number of channels constitutes a grouped conversion. packet scan
●The rule group consists of up to 16 conversions (16 channels). The regular channels and their conversion order are selected in the ADC_SQRx registers. The total number of conversions in the rule group should be written in the L[3:0] bits of the ADC_SQR1 register.
● Injection groups consist of up to 4 transitions. The injected channels and their conversion order are selected in the ADC_JSQR register. The total number of conversions injected into the group should be written in the L[1:0] bits of the ADC_JSQR register.
Conversion mode: 1 single conversion mode 2 continuous conversion mode 3 intermittent conversion (suitable for short sequence conversion) 4 scan conversion
Each ADC has 18 channels including 16 external channels, 2 internal channels, one internal temperature sensor and one internal reference voltage source channel
Supports left-aligned or right-aligned methods, and injects the calibration position