FPGA learning embedded hardware minimum system construction (1) (NIOS II processor settings)
The purpose of this study: Use the NIOS II system to light up the LCD1602 screen and 5.7-inch LCD (8080 interface).
Introduction
The previous article introduced an overview of embedded hardware systems, and mentioned that FPGA-based embedded systems are systems that can act as microprocessors. So what devices does an unprocessor system need?
The first is the most core MCU processor, so Altera provides a soft core processor NIOS core, this series of soft core is a 32-bit RISC embedded processor, with a performance of more than 200DMIP, a lot of advantages are listed in the manual. See the manual for details.
The most important thing here is that Altera provides the NIOS II development kit, which contains a set of general peripherals and interface libraries. Some IP and interfaces are shown in the following table. For details, please refer to the "Embedded Peripheral IP User Guide" manual.
And users can customize peripherals with special requirements that they need.
Because the LCD1602 component IP core exists in the NIOS II development kit in this study, there is no need to customize the IP core. After the LCD1602 is turned on, the 5.7-inch large screen will be lit, so I will focus on learning how to Go to customize your personal IP core.
NIOS II minimum system development process
First create the project, and then directly open the Qsys menu, the old version of Quartus is displayed as SOPC Builder.
Then you can see the overall page layout of Qsys. On the left is the component IP core library, and the blank part on the right is the area where we want to build the smallest system. In fact, to build the smallest system is to call the components in the component IP core library, and then connect these devices. Line, assign clock and address, etc. operations.
NIOS soft core processor introduction
Searching for NIOS in the component library will show the NIOS processor component,
【core Nios II】
We first number the home page that needs to be configured on the device home page.
Let’s start with [select a nios ii core] [serial number 2]: Here are the three cores and features of the Nios II system
Choose NIOS II/f here, the default is fine.
[Serial Number 3] is Hardware Arithmetic Operation, which is hardware arithmetic operation. Here you can choose the two options of embedded multiplier and logic element.
What is the difference between these two?
You can also choose whether to check Hardware divide hardware divider.
[No. 4] represents the reset vector [Reset Vector]
The above figure shows that there are 3 options for the reset vector setting.
According to the manual, the reset vector is actually selecting which non-volatile memory module reset code for the system.
[Serial Number 5] Represents the exception vector [Exception Vector]
According to the manual, it is found that the abnormal vector memory list is set to select the abnormal vector memory module. For example, in a typical system, a low-latency memory module is selected for the abnormal code.
[No. 6] indicates whether to enable "Include MMU", this setting will include Nios II MMU in the Nios II hardware system.
However, in the manual remarks, MMU is generally not selected unless required by the operating system (linux system), so generally we do not need to select settings.
[Caches and Memory Interfaces] [Caches and Memory Interfaces]
This page includes the setting of instruction cache and data cache,
【Instruction Master】
The following two pictures introduce the main functions of the three setting items of Instruction master and how to configure them.
【Data Master】
There are 6 options in [Data Master], the meanings are as follows:
Omit data master port---------Remove the Avalon-MM data master port from the Nios II processor. Only when the "Data Cache" is set to "None" and the number of tightly coupled data master ports is greater than zero, the port can be successfully deleted. Although the Nios II processor can run completely in tightly coupled memory without the need for Avalon-MM instructions or data hosts, if the Avalon-MM instructions or data hosts are omitted, software debugging is not possible.
data cache---------Specify the size of the data cache. The effective size is 512 bytes to 64 KB, or none.
According to the specified value of the data cache, there are the following option settings:
data cache line size---------The effective size is 4 bytes, 16 bytes or 32 bytes
Burst transfers---------Nios II processors can use burst transfers to fill their data cache lines. Generally, when processor data is stored in DRAM, bursts on the processor data bus are enabled, and when processor data is stored in SRAM, bursts are disabled.
Bursting to DRAM can usually improve memory bandwidth, but may consume additional FPGA resources. Please note that after bursting is enabled, access to the slave may be performed through other hardware (called burst adapters), which may reduce fMAX.
Burst is only enabled for data cache lines larger than 4 bytes. For a row size of 16 bytes, the burst length is 4; for a row size of 32 bytes, the burst length is 8. Data cache bursts are always aligned on cache line boundaries. For example, for a 32-byte Nios II data cache line, a cache miss to address 8 will result in bursts with the following address sequence: 0, 4, 8, 12, 16, 20, 24, and 28.
Number of tightly coupled data master port(s) (Include tightly coupled data master port(s))---------Specify 1-4 tightly coupled data master ports for the Nios II processor. In Qsys, select a number from the "Number of tightly coupled data master ports" list. The tightly coupled memory port appears on the connection panel of the Nios II processor on the Qsys system content tab. You must correctly connect each port to a memory component in the system. (It is consistent with the [Instruction Master] setting.)
[Advanced Features Tab] [Advanced Features Tab]
This page is the advanced function tab of the NIOS II processer, which can enable the special functions of the Nios II processor. Generally, I haven't managed it, and check for specific advanced functions.
[MMU and MPU Settings] This page setting tab is used to configure MMU and MPU on Nios II processor. The default is fine in the simple minimal system.
【JTAG Debug Module】
It can be seen that the JTAG Debug Module has four levels, and different levels of debugging consume different on-chip resources.
Since the memory such as SDRAM and RAM has not been set, after the minimum system starts to select the NIOS II processor, the options can be set as default, and the settings can be set after the later storage resources are added.