FPGA learning embedded hardware minimum system construction (two) (RAM, system_id and PIO, etc.)
The clock setting is not mentioned in the NIOS processor settings in the previous article. Generally, you need to configure the system clock before customizing your personal NIOS system. Because the crystal oscillator on the development board is 50MHz, the clock input to the system is the clock frequency of the external crystal oscillator, so here Set to 50MHz. There are two setting methods.
As can be seen from the above figure, the first one is to directly double-click clk_0 to modify the system clock, and the second one is to click clock settings to modify the system clock here.
In the previous article, we have described in detail how to customize the nios ii processor. This article will start directly from setting up the ROM and RAM. Later, when the LCD1602 is lit, SDRAM will be used instead of ROM.
Add ROM and RAM memory
Search ROM directly, and On-Chip Memory (RAM or ROM) appears, as shown in the figure below, so you know that RAM is still added here.
Find the manual. This IP core supports a variety of ROMs and ROMs. Here, if you choose a single-port ROM, you can use files for initialization.
There is one more read delay setting than the IP core setting in the previous FPGA system. Generally, the default setting is sufficient. Because the device resources are abundant, when single-port ROM and RAM are selected here, the default setting is sufficient, or you can select the initialization file enable.
RAM settings are the same. When we set up RAM and ROM, we can also add JTAG_UART debugger IP in the next step. Generally, this IP core is not selected when building the smallest system.
When customizing the NIOS II system, the system ID is essential
Refer to the manual as shown in the figure below. The system ID is indispensable, because it needs to provide a unique identifier for the NIOS II system. ID detection will be performed when connecting to the CPU. If the system ID is incorrect, the NIOS II system software cannot be normal Perform work.
The setting items are as follows, 32-bit system ID, you can set your own custom NIOS II system ID, or you can default it.
After adding the above IP core to the customized NIOS II system, the next step is to define our peripheral interface.
The importance of PIO core
Here we need to first understand the most important PIO core. The functions of the PIO core are as follows:
Each PIO core can provide up to 32 I/O ports. A host such as a microprocessor controls the PIO port through the Avalon-MM interface that reads and writes the register map. Under the control of the host, the PIO core captures data on its input and drives the data to its output. When the PIO port is directly connected to the I/O pin, the host can tri-state the pin by writing the control register in the PIO core. The manual shows a processor-based system that uses multiple PIO cores to drive LEDs, captures the edge of the on-chip reset request control logic and controls the off-chip LCD display.
In the system shown in the manual above, it can be seen that PIO can control the off-chip LCD liquid crystal display, because the learning goal of this period is to light up the LCD liquid crystal.
For example, I personally customize a minimal system to drive 8080 interface LCD liquid crystal, then what role does the PIO core play?
This involves the Avalon-MM bus interface, so the next article here focuses on the LCD1602 LCD IP core writing specifications and how to customize the 8080 interface LCD IP core in the smallest system.
It can be seen from the figure above that there are several IO types in the basic settings of PIO. The specific meanings are shown in the figure below. Different IOs correspond to the following different setting items.
It can be seen that when PIO acts as a data input, the Edge capture register and interrupt settings can be enabled.
[Edge capture register]
When Synchronously capture is turned on, the PIO core contains the edge capture register Edge Capture. The user must further specify the type of edge detection:
Rising Edge (rising edge)
Falling Edge
ANY Edge (rising and falling edge)
On the input port, when a specified type of edge occurs, the edge capture register allows the core to detect and (optionally) generate an interrupt.
When Synchronously capture is turned off, the Edge Capture register does not exist.
Enable Bit Clearing for Edge Capture Register
Turning on Enable bit-clearing for edge capture register allows you to clear the bits in one or more edge capture registers individually. For example, in order to clear the sixth bit of the edge capture register, you can write 01000000 to the register.
[Interrupt (interrupt)]
When a specified event occurs on the input port, turn on "Generate IRQ" to assert the IRQ output. And the reason for the IRQ event must be further specified:
• Level—The core generates an IRQ whenever a specific input is high and the input in the interrupt mask register enables interrupts.
Edge (edge)-whenever a specific bit in the edge capture register is high and an interrupt is enabled for that bit in the interrupt mask register, the core generates an IRQ.
When Generate IRQ is turned off, the interrupt mask register does not exist.
It can be seen that when PIO acts as a data output, the output register can be turned on.
The option Enable individual bit set/clear output register (Enable individual bit set/clear output register) option allows you to set or clear a single bit of the output port. After enabling this option, two additional registers (start register and clear register) will be implemented. You can use these registers to specify the output bits to be set and cleared.
As mentioned above, the PIO core settings are divided into data input or output to explain the configuration items. (The same applies to bidir and inout).
When these IP cores are added as shown in the figure above, basically the simple NIOS II system is established. Later learning will introduce how to connect these interface module lines and how to eliminate the error identification in the figure below.
But the next document will introduce how the LCD1602 core and PIO core files that come with the component library are written and how to customize and package your own 8080 interface LCD IP core.