cubemx configuration sdram

One, sdram introduction

SDRAM, the English name is: Synchronous Dynamic Random Access Memory, that is, synchronous dynamic random access memory. Compared with SRAM (static memory), SDRAM has the characteristics of large capacity and low price.

Two, W9825G6KH chip introduction

2.1 The internal structure of the chip

The internal structure of the chip is as shown below

2.2 Chip pin description

• CLK: Clock signal, collect the input signal on the rising edge of the clock
• CKE: Clock enable, when the clock is disabled, SDRAM will enter self-refresh mode
• CS: Chip select signal, active low
• RAS: Row address strobe signal, when low level, it means row address
• CAS: Column address strobe signal, when low level, indicates the column address
• WE: Write enable signal, active low
• A0~A12: Address line (row/column)
• BS0, BS1: BANK address line
• DQ0~15: data line
• LDQM, UDQM: data mask, representing the effective part of DQ

2.3 The working principle of the chip

2.3.1 Addressing

• First, the RAS signal is low level, the row address is strobed, and the address represented by the address lines A0~A12 will be transmitted and latched into the row address decoder as the row address. At the same time, the BS0 and BS1 on the BANK address line The indicated BANK address will also be latched, and the corresponding BANK will be selected.
• Then, the CAS signal is low, the column address is strobed, and the address represented by the address lines A0~A12 will be transmitted and latched into the column address decoder as the column address. In this way, an address is completed. .
  Summary: During RAS low level, select BANK and row address; during CAS low level, select column address.

2.3.2 Data Transmission

After addressing, you can read and write data in sdram.

Three, cubemx configuration

W9825G6KH address lines A0~A12 have 13 bits in total, and there are 4 banks inside, and data from DQ0 to DQ15 are 16 bits in total. Here, two W9825G6KH pieces are used to form 32 bits. Each piece provides 32M bytes of sdram, and two pieces can provide 64M bytes. Sdram.

The column address A0-A8 has a total of 9 bits, and the row address A0-A12 has a total of 13 bits.

Configure the delay parameters of W9825G6KH as follows:

Fourth, the use of sdram

Initialization sequence

//SDRAM配置参数
#define SDRAM_MODEREG_BURST_LENGTH_1             ((u16)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2             ((u16)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4             ((u16)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8             ((u16)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((u16)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((u16)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2              ((u16)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3              ((u16)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((u16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((u16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((u16)0x0200)
//发送命令函数，下面的初始化时序需要使用
u8 SDRAM_Send_Cmd(u8 bankx,u8 cmd,u8 refresh,u16 regval)
{
    
    
    u32 target_bank=0;
    FMC_SDRAM_CommandTypeDef Command;
    
    if(bankx==0) target_bank=FMC_SDRAM_CMD_TARGET_BANK1;       
    else if(bankx==1) target_bank=FMC_SDRAM_CMD_TARGET_BANK2;   
    Command.CommandMode=cmd;                //命令
    Command.CommandTarget=target_bank;      //目标SDRAM存储区域
    Command.AutoRefreshNumber=refresh;      //自刷新次数
    Command.ModeRegisterDefinition=regval;  //要写入模式寄存器的值
    if(HAL_SDRAM_SendCommand(&hsdram1,&Command,0XFFFF)==HAL_OK) //向SDRAM发送命令
    {
    
    
        return 0;  
    }
    else return 1;    
}
//发送SDRAM初始化序列
void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram)
{
    
    
	u32 temp=0;

    //SDRAM控制器初始化完成以后还需要按照如下顺序初始化SDRAM
    SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_CLK_ENABLE,1,0); //时钟配置使能
    HAL_Delay(1);                                  //至少延时200us
	SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_PALL,1,0);       //对所有存储区预充电
    SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_AUTOREFRESH_MODE,8,0);//设置自刷新次数 
    //配置模式寄存器,SDRAM的bit0~bit2为指定突发访问的长度，
	//bit3为指定突发访问的类型，bit4~bit6为CAS值，bit7和bit8为运行模式
	//bit9为指定的写突发模式，bit10和bit11位保留位
	temp=(u32)SDRAM_MODEREG_BURST_LENGTH_4          |	//设置突发长度:1(可以是1/2/4/8)
              SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |	//设置突发类型:连续(可以是连续/交错)
              SDRAM_MODEREG_CAS_LATENCY_2           |	//设置CAS值:2(可以是2/3)
              SDRAM_MODEREG_OPERATING_MODE_STANDARD |   //设置操作模式:0,标准模式
              SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;     //设置突发写模式:1,单点访问
    SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_LOAD_MODE,1,temp);   //设置SDRAM的模式寄存器
    
    //刷新频率计数器(以SDCLK频率计数),计算方法:
	//COUNT=SDRAM刷新周期/行数-20=SDRAM刷新周期(us)*SDCLK频率(Mhz)/行数
    //我们使用的SDRAM刷新周期为64ms,SDCLK=200/2=100Mhz,行数为8192(2^13).
	//所以,COUNT=64*1000*100/8192-20=677
	HAL_SDRAM_ProgramRefreshRate(hsdram,677);	
}	

Test function

#define Bank5_SDRAM_ADDR    ((uint32_t)(0XC0000000)) //SDRAM开始地址
u16 testsram[250000] __attribute__((at(0XC0000000)));//测试用数组
//SDRAM内存测试	    
for(cnt=0;cnt<250000;cnt++)
{
    
    
	testsram[cnt]=cnt;					 
}
for(ts=0;ts<250000;ts++)
{
    
    
	printf("testsram[%d]:%d\r\n",cnt,testsram[cnt]);
}

Output result
Print out the data of the array stored in sdram, we can define the data in sdram through __attribute__, this is the usage of sdram.

Reference example

My code cloud address: cubemx configuration sdram routine