SDRAM from development up to now has gone through five generations, namely: the first generation of SDR SDRAM, the second generation of DDR SDRAM, the third generation of DDR2 SDRAM, the fourth generation of DDR3 SDRAM, a fifth-generation DDR4 SDRAM. The first generation of single-end SDRAM (Single-Ended) clock signal, second generation, third generation and fourth generation since the operating frequency is faster, so the differential clock signal may be used as the synchronous clock to reduce interference. SDR SDRAM clock frequency is the frequency of the data storage, the data is also read and write rates of 100 or 133MHz.
Memory chip want to work, it must be associated with the memory controller, for a while electrical components, power supply is also essential, and the transmission of data as a trigger to have a clock reference. Thus when the package on the SDRAM corresponding pin set aside for use. Power and clock pins do not have to say, imagine that there should be control pins it?
Thread from memory addressing step down basically to understand, which will be able to understand the general situation of working memory. It should be noted here that SDRAM has its own industry design specifications, in the capacity of a standard pin / signal standard SDRAM can not just consider a bit wide design, but to take into account a variety of bits wide, and then try to give a common standards, little bit wide chip line will also empty out some pins, but the high-bit-wide chips might all spend. But not the same capacity, design standards will be different, the general capacity of the smaller chip will require less pins.
(1) First, we know that first determines a memory controller chip, the chip and fishes addressing operation. Therefore to have a chip select signal, which selects the chip. Selected chip received or read data, so there must be a chip select signal.
(2) Next, the selected chip of the same L-Bank address currently SDRAM L-Bank of the number of a maximum of four, so two L-Bank address signals.
Line (3) The final step is to select the same chip / column addressing. The number of address lines according to the organizational structure of the chip are designed. However, in the same capacity, the number of rows is the same, only the number of columns will vary depending on the bit width, the larger the bit width of the less number of columns because the required memory cells has been reduced.
(4) After locating the storage unit, the selected device will be uniform data transfer, then the bit width sure to have the same number of data I / O channel for the job, so it must have the appropriate number of data bus pins.