[Electronic Technology] [2017] Hardware implementation and design space exploration of Wave 2D and Jacobi 2D template calculation

This article is Colorado State University (Author: Rajbharath Chandramohan) master's thesis, a total of 65.

Hardware accelerators are highly optimized functional modules designed to perform specific tasks with higher performance. We have developed a hardware accelerator for the Jacobi 2D and Wave 2D algorithms, both of which use template mode for calculation. They are used in many scientific applications in the fields of acoustics, electromagnetics, and fluid mechanics. These problems have large problem solving, memory limitations, and bandwidth limitations, which lead to long running times. Therefore, it is necessary to adopt a method to improve the performance of solving these problems, thereby reducing bandwidth requirements.

We established the analysis models of Wave-2D algorithm and Jacobi-2D algorithm performance, bandwidth and area, and solved them with MATLAB and Excel. In order to achieve the best design, we divide the calculation into two levels. The first layer is called passes, which is a cuboid that passes through the three-dimensional iterative space. Each process is mapped to the processing element (PE) grid in the hardware accelerator. The second level of tiling splits the vertical cuboid into smaller cuboids performed by a single PE. These optimizations were implemented in a hardware accelerator designed with Verilog and simulated with ModelSIM. ModelSIM simulation results provide an accurate model and design experimental verification. We have also improved processing performance and reduced bandwidth.

Hardware accelerators are highly optimized functional blocks designed to perform specific tasks at higher performance. We developed a hardware accelerator for Jacobi 2D and Wave 2D algorithms, two computations with a stencil pattern. They are used in many scientific applications in the field of acoustics, electro magnetics and Fluid dynamics. These problems have large problem sizes, memory limitations and bandwidth constraints that result in long run times. Hence, an approach which increases the performance of these problems that reduces bandwidth requirement is necessary. We developed analytical models for the performance, bandwidth and area models for the Wave 2D algorithm and Jacobi 2D algorithm and solved them for the optimal solution using posynomials and positivity property in MATLAB and using Excel Solver. In order to achieve an optimal design, we split the computation into two levels of tiling. The first level called passes is a rectangular prism that runs through the 3-D iteration space. Each pass is mapped to a grid of processing elements(PEs) in the hardware accelerator. The second level of tiling splits the vertical prism into smaller prisms executed by a single PE. These optimizations are implemented in the hardware accelerator designed using Verilog and simulated using ModelSIM. Results from ModelSIM provides an accurate model and an experimental verification of the design. We also achieved improved performance and lower bandwidth.

1.   引言
   

2. Background of the project
3. Wave 2D accelerator design
4. Jacobi 2D accelerator design
5. hardware design
6. Optimization problem
7. Conclusion and Outlook

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