[Operating system design principles and essence of notes] Chapter1 Computer System Overview

Chapter1 Computer System Overview

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1.1 basic configuration

1. Four major structural components: a processor, main memory, input / output modules, a system bus

2. The processor exchanges data with a memory: MAR, MBR

   The processor and the input / output module to exchange data: I / O AR, I / O BR

   Processor PC, IR

   

1.2 Microprocessor Development

Slightly

1.3 instruction execution

1. Cycles: fetch stage, execution stage

2. The program counter PC, the instruction register IR

3. Four main operation instructions: data transmission processor and memory, the processor and the input / output module data transfer, data processing (processor performs arithmetic and logic operations), the control (changing the execution order)

4. example (comprising a processor and the memory data transfer, data processing)

   

(1) PC = 300, the processor 300 from the memory address of the instruction fetch unit 1940, the instruction into IR, PC is incremented to 301

(2) execute the instruction, the processor 940 of the memory cell address is taken from the 0003 data, in the accumulator AC

(3) PC = 301, processor instruction fetch unit 301 of the memory 5941, the address from the instruction into IR, PC is incremented to 302

(4) to execute the instruction, the processor 941 takes the data memory unit 0002, adds the data from the address AC, the result back to AC

(5) PC = 302, the processor 302 from the memory address instruction fetch unit 2941, the instruction into IR, PC is incremented to 303

(6) executing the instruction, the processor stores the address data AC, the memory cells 941

1.4 Interrupt

1. Common interrupt Category: interrupt, timer interrupt, I / O interrupts, hardware interrupts failure

2. Instruction cycle
   

3. Long I / O wait and the short timing analysis program I / O wait

4. Software and hardware interrupt event processing

5. Multiple interrupt

   (1) when handling an interrupt, the interrupt occurs again ban

   (2) the definition of interrupt priority, high priority interrupts to allow low-priority interrupt operation

Memory hierarchy 1.5

1. The design goal of computer memory: a trade-off between speed, capacity and price
2. Memory Hierarchy
   

Storage hierarchy from the top down: a processor registers, cache, memory, disk

(1) decreasing the price per bit

(2) decreasing access speed

(3) incremental capacity

(4) decreasing the frequency of access to the processor

1.6 Cache

1. Significance cache: processor speed instructions executed by the storage period limit, the speed and cost trade-off, considering the use of the principle of locality, a small increase of memory capacity and speed between registers and memory

2. Locality principle: the block transfer between the cache and memory

3. The use of multi-level cache
   

4. principle

   (1) Memory capacity $2^n$ words, each block (block) comprising K words, a total of $M=2^n/K$blocks

   (2) C cache memory has slots (slots), each groove K words and a tag (block stored identification)

   (3) (word processor read address RA), the read word processor, if RA contains blocks not in the cache , the processor accesses the memory blocks included in the RA, assigned cache slot then loading the memory block cache slot, while the RA of the word transfer to the CPU; block if RA is contained in the cache , direct access to the RA of the word to the CPU

1.7 Direct Memory Access

1. Performing I / O operations in the art: a programmable I / O, interrupt driven I / O, direct memory access (DMA)

   (1) a programmable I / O operations: a processor to I / O module after commanding to execute instructions, to periodically check the status to determine if the I / O operation is completed, the processor to wait a long time

   (2) Interrupt driven I / O

2. Direct memory access (DMA, direct memory access)

   (1) When the processor sends an instruction, the DMA transfer DMA module directly with the memory module entire block of data, a DMA module sends an interrupt signal to the processor after the completion of

   Instruction (2) sent to the DMA processor module comprises: a read address start whether a request operation, I / O devices, memory cells, reading and writing of words

And a multi-core processor computer over 1.8 Structure

1. Symmetric Multi-Processor (SMP)

   (1) Definition: a plurality of comparable performance processor, shared memory, and I / O devices (through the system bus), shared access to I / O devices, perform the same function, a unified operating system control, operation can be performed , processes, files and other data element level of interaction

   (2) compared with a single processor

   1) performance
   2) Availability: single processor failure will not result in downtime
   3) incremental growth
   4) Scalability

   (3) Structure
   

   Cache coherency problem is usually solved by hardware

2. Multicore computer: a plurality of processors (core) is assembled on a single silicon computer (sheet), also known as a chip multiprocessor