Experiments have been over 70 years of complex instructions, may be used an interpreter to do. Designers try to reduce the semantic gap "machine can do" and "what needs to be high-level language" between. Almost no one considered the design simpler machines, as now there is not much research on how to design low-power concern spreadsheet capacity, network, Web servers, and so on.
One group against this trend, trying to absorb Seymour Cray philosophy on high-performance computers, the group leader is IBM's John Cocke. These efforts led to the birth of a microcomputer experimental nature, it is 801. Although IBM has never produced the machine, and was only released after years of research results (Radin, 1982), but after news of the others started to invest a similar architecture.
In 1980, a led by David Patterson and Carlo tournament Kun, located Pericles organization began to design VLSI CPU chip, without the use of an interpreter (Patterson, 1985, Patterson and race-kun , 1982). They created the concept for the term RISC, and their CPU chip named RISC I CPU, followed by RISC II. Later, in 1981, Stanford, San Francisco Bay, John Hennessy designed and created a little different chips, is referred to as MIPS (Hennessy, 1984). These chips are developed into products with great value commercially, SPARC and MIPS and then go their way.
These new processors and processor business was very different. Since they are not backward compatible with existing products, their designer can be free to choose a new set of instructions to maximize overall system performance. Although the initial focus is how to make simple and fast execution of instructions, they soon realized quickly start instruction is the key to enhance performance. An instruction how long the actual implementation of the directive can not start the second important number.
At that time these simple processors are designed to be the first time, striking feature is relatively much less available instructions, generally about 50. This figure has more than 200 computers to Article 300 is much smaller, such as DEC VAX and IBM large commercial aircraft. In fact, is spelling the acronym RISC Complex Instruction Set Computer (slimmed-VAX, VAX then ruled the Department of Computer universities). Few people today feel the scale of the instruction set is a major problem, but RISC name or handed down.
Long story short, with RISC supporters attack on the established order (VAX, Intel, IBM large commercial aircraft), and a great religious war broke out. They claim that the best way is to use the design computer few simple instructions, data path in FIG Fg2-2 (two registers, in some combination thereof) to perform one cycle, and then the result is stored back in the register. Their argument is: Even if a machine CISC RISC instruction is worth four or five, if the RISC instruction 10 times faster (because they do not explain), RISC also won. It should be noted that the main memory of today has caught up with the speed control read-only memory, so the sharp increase in side effects interpreter, which is very beneficial for the RISC machines.
One might think that, as you say, RISC technology rolling round in the commercial RISC machine (such as Sun UltraSPARC) should CISC machines (such as the Intel Pentium series) dry down the fishes. But there is no sign that this, why?
First of all, there are backward compatibility issues, and billions of dollars have been invested in Intel's production line. Then, amazing is that Intel has the ability to use the same idea, even CISC architecture. From the start 486, an Intel CPU RISC core comprising, for performing the most simple (and often also the most common) instruction in a simple data path cycle, while more complex instructions that explain a CISC manner. The end result is a universal command quickly, non-generic instructions slowly. While this hybrid approach is better pure RISC designed to run faster, the ability to make it compatible with older software that can run without modification.