Analog Circuit

Note of Analog Circuit
Book: Microelectronic Circuits by Sedra Smith

Norton and Thevenin Circuit

Find Equivalent $R_{eq}$:

1. Apply test source $V_T$
2. Measure test current $I_T$
3. $R_{eq}$ = $V_T/I_T$.

Thevenin:

1. $V_{TH} = V_{OC}$
2. zero out independent sources (0 voltage = short circuit, 0 amplititude = open circuit)
3. Find $R_{TH}$

Norton:

1. $I_N=V_{TH}/R_{TH}, R_N=R_{TH}$
2. or short circuited, $I_N=I_{OC}$

Amplifiers

Generic circuit model of Linear Amplifier

$R_{in} =$ input resistance
$R_{out} =$ output resistance
$A_{vo} =$ open loop voltage gain
*Note: Linear amplifier will not change the frequency of input voltage.

$\dfrac{v_o}{v_s} = A_{vo}\dfrac{R_{in}}{R_{in}+R_s}\dfrac{R_{L}}{R_{L}+R_{out}}$

desire: large $R_{in}$, small $R_{out}$, large $A_{vo}$

Laplace Transform

A signal can be considered as considered as superpostion of many sinusoids.
Time domain: $v(t)=v_0\cos(\omega t+\phi)$
Frequency domain: Real part of $v_0 \angle \phi$

The formula for Laplace transform is:
$F(s)=\int_{t=0^-}^{+\infty}f(t)e^{-st}\mathrm{d}t,$where $s=j\omega$, with requirement:

• Integral must converge
• $f(t<0)=0$

properties	Equation
Time dreivative	$f'(t) \Leftrightarrow sF(s)-f(0^+)$
Convolution	$F_1(s)F_2(s)\Leftrightarrow (f_1*f_2)(t)=\int_0^tf_1(\tau)f_2(t-\tau)\mathrm{d}t$
Initial value theorem	$f(0^+)=\lim_{s\rightarrow\infty}sF(s)$
Final value theorem	$f(\infty)=\lim_{s\rightarrow0}sF(s)$

In frequency domain,
the impedance of L and C is
L: Ls
C:1/(Cs)

Bode Plot

How to draw bode plot:

Sallen & Key Method to Design Circuit

Essential Equation:
$T_1 = R_1C_1\omega_0$
$T_2 = R_2C_2\omega_0$

Non-ideal Op-amps

Ideal Op-amp

Based on the Op-amp model, there are 3 assumptions:

1. $A_0\rightarrow \infty \Rightarrow v_+=v_-$
2. $R_{in} = \infty \Rightarrow i_{in}=0$
3. $R_{out}=0 \Rightarrow$ no voltage drop across $R_{out}$

3 basic configuration:

name	equ	Figure.
Inverting amplifier	$\dfrac{v_{out}}{v_{in}}=-\dfrac{R_2}{R_1}$
Non-inverting	$\dfrac{v_{out}}{v_{in}}=1+\dfrac{R_2}{R_1}$
voltage folower	$\dfrac{v_{out}}{v_{in}}=1$

Non-ideal Op-amp

1. Finite open-loop gain
   Non inverting: feed back factor $f=\dfrac{R_1}{R_1+R_2}$, $v_{out}/v_{in}=\dfrac{A_0}{1+A_0f}$
   Inverting: $G=\dfrac{-R_2/R_1}{1+(1+R_2/R_1)/A_0}$
2. Finite $R_{out}\neq0$
   Turn off the input voltage source and find $R'_{out}$
   Non-inverting amplifier: $R'_{out}=\dfrac{R_{out}}{1+A_0f}$
3. Finite $R_{in}$
   $i_+=i_-\neq0$
4. Common mode rejection ratio CMRR
   $v_{id}=v_+-v_-$
   $v_{ic}=\dfrac{v_++v_-}{2}$
   $v_{out}=A_0[v_{id}+\dfrac{v_{ic}}{CMRR}]$, $CMRR=\dfrac{A_0}{A_{cm}}$
   Voltage follower: $\dfrac{v_{out}}{v_{in}}=\dfrac{A_0(1+1/2CMRR)}{1+A_0(1-1/2CMRR)}$
   Application: Difference Amplifier
   
   The circuit can be solved with superposition. To make it a differential amplifier, we ensure that $\dfrac{R_2}{R_1}=\dfrac{R_4}{R_3}$, through calculation, $A_d=\dfrac{R_2}{R_1}$.
   If $v_{I1}=v_{I2}=v_{Icm}$,
5. Input Offset Voltage
   Model the residual $v_{out}$ when $v_{in}=0$ as a source at the input +:
   
   Modified $v_{out}=A_0[v_{id}+\dfrac{v_{ic}}{CMRR}+v_{os}]$
   *this can be trimmed to zero by connecting a potentiometer to the two offset-nulling terminals.
   
6. Input bias current
   
   $I_{B1}, I_{B2}$ are small constant current, $I_{B1}\neq I_{B2}$. Not the same as $i_{in}$.
   $I_B=\dfrac{I_{B1}+I_{B2}}{2}$
   $I_{OS}=|I_{B1}-I_{B2}|$
7. Clipping
   Output is limited by $+V_{CC}$ and $-V_{EE}$, introduce other frequency component.
8. Bandwidth
   Open loop condition:
   open loop gain is frequency dependent
   $A(s)=\dfrac{A_0}{1+s/\omega_p}$
   $\omega_t$= frequency when $|A|=1$
   $f_t$=unity gain bandwidth
   Suppose $\omega_t \gg \omega_p$, we have $\omega_t=A_0\omega_p$
   Closed loop condition
   For inverting circuit:
   
   Assume $A_0\gg 1+\dfrac{R_2}{R_1}$, can get rid of the mid term. $\omega_{3dB}=\dfrac{\omega_t}{1+R_2/R_1}$
   For non-inverting circuit:
   
   Note: gain-bandwidth product = $f_t$.
9. Slew rate
   Come from the finite current available to charge and discharge internal capacitance.
   $SR=\dfrac{\mathrm{d}v_0}{\mathrm{d}t}|_{\mathrm{max}}$
   Simple example: if $v_{out}(t) = v_m\sin(\omega t)$, $SR\geq max(v'_{out}(t))=v_m\omega$

Internal of an Op-amp

$v_3=\mu G_m R(v_2-v_1)$

Diodes

p type (acceptor): positive charge carrier, releases as a “hole”. e.g. Boron(+3)
n type (donor): negative charge carrier, mobile electron, e.g. Phosphorous(+5)
concentration: number of charge carriers per unit volume( $[cm^{-3}]$)

PN junction diode

p type region has extra hole, and q type region has extra electron.

1. The hole will be filled with electrons gradually due to diffusion. The middle area is already charged, called depletion or space charge region.
2. An electromagnetic field formed. A built-in voltage was introduced, which stops diffusion.
   $E_{max}=\dfrac{qN_Dx_n}{\epsilon_s\epsilon_0}=\dfrac{qN_Ax_p}{\epsilon_s\epsilon_0}$, $\epsilon_s=$electrical permittivity of silicon
   $W=x_n+x_p=\sqrt{\dfrac{2\epsilon_s\epsilon_0}{q}(1/N_A+1/N_D)(v_{bi}-v_A)}$
   $v_{bi}=\dfrac{k_BT}{q}\ln(\dfrac{N_DN_A}{n_i^2})$
3. Apply positive voltage to p side, when $v_A>v_{bi}$, there will be no depletion area and large current can flow.
4. When a very large negative voltage applied, the junction will break down due to zener effect.
5. The I-V relation:
   $I_D=I_S[e^{qv_D/nkT}-1]\approx I_Se^{v_D/v_T}=(\text{under room temperature})I_S[e^{v_D/0.0258}-1]$

Temperature Dependency

1. Forward Bias $I_S$: doubles every $5^\circ C$ raise in temperature
   [Approximately Equivalent: $V_D$ decreases by $10mV$, not very accurate]
2. Reverse Bias $-I_R$: doubles for every $10^\circ C$ raise in temperature
   $I_D\approx-I_R$(independent of voltage)

Solve Circuits with Diode

1. Guess region
2. Solve circuit
3. Check Assumption

Usage

1. Half-wave Rectifier
2. Full-wave Rectifier
3. Peak detector
4. RC Load-peak Rectifier