xilinx官方提供的spartan 3 starter kit有两片ISSI 256Kx16位的SRAM，这两个SRAM复用地址线，数据线都引入到FPGA，因此，FPGA访问外部SRAM的位宽是32位，基于该开发板，使用XPS设计嵌入式系统使用xilinx默认的配置32位宽。但是对于某些应用，fpga引脚是稀缺资源，因此32位宽不可能实现，此时需要使用8位或者16为的SRAM（ISSI提供8、16、32位的高速异步SRAM芯片）。本文阐述了，使用emc ip core连接16位SRAM的例子。本文只使用开发板上两片SRAM中的一片（IC11）。
system.mhs
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Sun Dec 14 15:48:49 2008
# Target Board: Xilinx Spartan-3 Starter Board Rev E
# Family: spartan3
# Device: XC3S200
# Package: FT256
# Speed Grade: -4
# Processor: microblaze_0
# System clock frequency: 50.00 MHz
# On Chip Memory : 8 KB
# Total Off Chip Memory : 1 MB
# - SRAM = 1 MB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [13:30]
PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:15]
PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0]
PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0]
PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O
PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:1]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_INTERCONNECT = 1
PARAMETER HW_VER = 7.10.d
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_AREA_OPTIMIZED = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
PORT MB_RESET = mb_reset
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.03.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN xps_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.00.a
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_RX
PORT TX = fpga_0_RS232_TX
END
BEGIN xps_mch_emc
PARAMETER INSTANCE = SRAM
PARAMETER HW_VER = 2.00.a
PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
PARAMETER C_TCEDV_PS_MEM_0 = 10000
PARAMETER C_TWC_PS_MEM_0 = 8000
PARAMETER C_TAVDV_PS_MEM_0 = 10000
PARAMETER C_TWP_PS_MEM_0 = 8000
PARAMETER C_MEM0_BASEADDR = 0x84100000
PARAMETER C_MEM0_HIGHADDR = 0x8417ffff
PARAMETER C_MEM0_WIDTH = 16
PARAMETER C_MAX_MEM_WIDTH = 16
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
BUS_INTERFACE SPLB = mb_plb
PORT Mem_A = fpga_0_SRAM_Mem_A_split
PORT Mem_DQ = fpga_0_SRAM_Mem_DQ
PORT Mem_OEN = fpga_0_SRAM_Mem_OEN
PORT Mem_CEN = fpga_0_SRAM_Mem_CEN
PORT Mem_WEN = fpga_0_SRAM_Mem_WEN
PORT Mem_BEN = fpga_0_SRAM_Mem_BEN
PORT RdClk = sys_clk_s
END
BEGIN util_bus_split
PARAMETER INSTANCE = SRAM_util_bus_split_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 32
PARAMETER C_LEFT_POS = 13
PARAMETER C_SPLIT = 31
PORT Sig = fpga_0_SRAM_Mem_A_split
PORT Out1 = fpga_0_SRAM_Mem_A
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 50000000
PARAMETER C_CLKOUT0_FREQ = 50000000
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PORT CLKOUT0 = sys_clk_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END
BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 1.00.d
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Peripheral_Reset = sys_periph_reset
END
======================
system.ucf
############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################
Net sys_clk_pin LOC=T9;
Net sys_rst_pin LOC=l14;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
Net sys_rst_pin TIG;
## IO Devices constraints
#### Module RS232 constraints
Net fpga_0_RS232_RX_pin LOC=t13;
Net fpga_0_RS232_TX_pin LOC=r13;
#### Module SRAM constraints
Net fpga_0_SRAM_Mem_A_pin<30> LOC=l5;
Net fpga_0_SRAM_Mem_A_pin<29> LOC=n3;
Net fpga_0_SRAM_Mem_A_pin<28> LOC=m4;
Net fpga_0_SRAM_Mem_A_pin<27> LOC=m3;
Net fpga_0_SRAM_Mem_A_pin<26> LOC=l4;
Net fpga_0_SRAM_Mem_A_pin<25> LOC=g4;
Net fpga_0_SRAM_Mem_A_pin<24> LOC=f3;
Net fpga_0_SRAM_Mem_A_pin<23> LOC=f4;
Net fpga_0_SRAM_Mem_A_pin<22> LOC=e3;
Net fpga_0_SRAM_Mem_A_pin<21> LOC=e4;
Net fpga_0_SRAM_Mem_A_pin<20> LOC=g5;
Net fpga_0_SRAM_Mem_A_pin<19> LOC=h3;
Net fpga_0_SRAM_Mem_A_pin<18> LOC=h4;
Net fpga_0_SRAM_Mem_A_pin<17> LOC=j4;
Net fpga_0_SRAM_Mem_A_pin<16> LOC=j3;
Net fpga_0_SRAM_Mem_A_pin<15> LOC=k3;
Net fpga_0_SRAM_Mem_A_pin<14> LOC=k5;
Net fpga_0_SRAM_Mem_A_pin<13> LOC=l3;
Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=p2;
Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=n2;
Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=m2;
Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=k1;
Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=j1;
Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=g2;
Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=e1;
Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=d1;
Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=d2;
Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=e2;
Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=g1;
Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=f5;
Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=c3;
Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=k2;
Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=m1;
Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=n1;
Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=k4;
Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=n5;
Net fpga_0_SRAM_Mem_WEN_pin LOC=g3;
Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=p5;
Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=r4;