1.题目
2.源码
三段式状态机
// *********************************************************************************
// Project Name : Sequence_detection
// Email : [email protected]
// Website : https://home.cnblogs.com/u/hqz68/
// Create Time : 2019/12/14
// File Name : Sequence_detection.v
// Module Name : Sequence_detection
// Abstract :
// editor : sublime text 3
// *********************************************************************************
// Modification History:
// Date By Version Change Description
// -----------------------------------------------------------------------
// 2019/12/14 宏强子 1.0 Original
//
// *********************************************************************************
`timescale 1ns/1ns
module Sequence_detection (
//system signals
input sclk , //10m
input s_rst_n ,
//input
input [1:0] s ,
//output
output reg [1:0] z
);
//========================================================================\
// =========== Define Parameter and Internal signals ===========
//========================================================================/
localparam s00 = 4'd0 ;
localparam s01 = 4'd1 ;
localparam s11 = 4'd2 ;
localparam s12 = 4'd3 ;
localparam s13 = 4'd4 ;
localparam s14 = 4'd5 ;
localparam s15 = 4'd6 ;
localparam s16 = 4'd7 ;
localparam s21 = 4'd8 ;
localparam s22 = 4'd10 ;
localparam s23 = 4'd11 ;
localparam s24 = 4'd12 ;
localparam s25 = 4'd13 ;
localparam s26 = 4'd14 ;
reg [3:0] state ;
reg [3:0] next_state ;
//=============================================================================
//**************************** Main Code *******************************
//=============================================================================
//使用三段式状态机
always @ (posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
state <= s00;
else
state <= next_state;
end
always @ (*) begin
case(state)
s00:begin
if (s == 2'b00)
next_state = s01;
else
next_state = state;
end
s01:begin
if (s == 2'b01)
next_state = s11;
else if (s == 2'b10)
next_state = s21;
else if (s == 2'b11)
next_state = s00;
else
next_state = state;
end
s11:begin
if (s == 2'b11)
next_state = s12;
else if (s == 2'b00)
next_state = s01;
else if (s == 2'b10 | s == 2'b01)
next_state = s00;
else
next_state = state;
end
s21:begin
if (s == 2'b11)
next_state = s22;
else if (s == 2'b00)
next_state = s01;
else if (s == 2'b10 | s == 2'b01)
next_state = s00;
else
next_state = state;
end
s12:begin
if (s == 2'b10)
next_state = s13;
else if (s == 2'b00)
next_state = s01;
else if (s == 2'b11 | s == 2'b01)
next_state = s00;
else
next_state = state;
end
s22:begin
if (s == 2'b01)
next_state = s23;
else if (s == 2'b00)
next_state = s01;
else if (s == 2'b11 | s == 2'b10)
next_state = s00;
else
next_state = state;
end
s13:begin
if (s == 2'b00)
next_state = s14;
else if(s != 2'b00)
next_state = s00;
else
next_state = state;
end
s23:begin
if (s == 2'b00)
next_state = s24;
else if(s != 2'b00)
next_state = s00;
else
next_state = state;
end
s14:begin
if (s == 2'b01)
next_state = s15;
else if (s == 2'b00)
next_state = s01;
else if (s == 2'b11 | s == 2'b10)
next_state = s00;
else
next_state = state;
end
s24:begin
if (s == 2'b10)
next_state = s25;
else if (s == 2'b00)
next_state = s01;
else if (s == 2'b11 | s == 2'b01)
next_state = s00;
else
next_state = state;
end
s15:begin
if (s == 2'b11)
next_state = s16;
else if (s == 2'b00)
next_state = s01;
else if (s == 2'b01 | s == 2'b10)
next_state = s00;
else
next_state = state;
end
s25:begin
if (s == 2'b11)
next_state = s26;
else if (s == 2'b00)
next_state = s01;
else if (s == 2'b01 | s == 2'b10)
next_state = s00;
else
next_state = state;
end
s16:begin
if (s == 2'b10)
next_state = s13;
else if (s == 2'b00)
next_state = s01;
else if (s == 2'b11 | s == 2'b01)
next_state = s00;
else
next_state = state;
end
s26:begin
if (s == 2'b01)
next_state = s23;
else if (s == 2'b00)
next_state = s01;
else if (s == 2'b11 | s == 2'b10)
next_state = s00;
else
next_state = state;
end
default : next_state = s00;
endcase
end
always @ (posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
z <= 2'b00;
else if(next_state == s16)
z <= 2'b10;
else if(next_state == s26)
z <= 2'b11;
else
z <= 2'b00;
end
endmodule3.测试平台
`timescale 1ns/1ns
module tb_sim();
reg sclk ;
reg s_rst_n ;
reg [1:0] s ;
wire [1:0] z ;
initial begin
sclk = 1;
s_rst_n = 0;
s = 2'b11;
#200
s_rst_n = 1;
#100
s = 2'b00;
#100
s = 2'b01;
#100
s = 2'b11;
#100
s = 2'b10;
#100
s = 2'b00;
#100
s = 2'b01;
#100
s = 2'b11;
#100
s = 2'b10;
#100
s = 2'b00;
#100
s = 2'b01;
#100
s = 2'b11;
#100
s = 2'b00;
#100
s = 2'b10;
#100
s = 2'b11;
#100
s = 2'b01;
#100
s = 2'b00;
#100
s = 2'b10;
#100
s = 2'b11;
#100
s = 2'b01;
#100
s = 2'b00;
#100
s = 2'b10;
#100
s = 2'b11;
end
always #50 sclk = ~sclk;
Sequence_detection Sequence_detection_inst(
//system signals
.sclk (sclk ), //10m
.s_rst_n (s_rst_n ),
//input
.s (s ),
//output
.z (z )
);
endmodule4.仿真波形
