重温FPGA之自动咖啡售卖机 verilog实现

1.题目

2.源码

// *********************************************************************************
// Project Name : auto_caffe_teller
// Email        : [email protected]
// Website      : https://home.cnblogs.com/u/hqz68/
// Create Time  : 2019/12/12 
// File Name    : auto_caffe_teller.v
// Module Name  : auto_caffe_teller
// Abstract     :
// editor		: sublime text 3
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2019/12/12    宏强子           1.0                     Original
//  
// *********************************************************************************
`timescale      1ns/1ns
module auto_caffe_teller (
	//system signals
	input					sclk			, 
	input					s_rst_n			, 
	//Cancel key
	input					Cancel_key		,
	//Taste choice key
	input			[3:0]	Taste_key		,
	//Coin input
	input					Coin_10			,
	input					Coin_5			,
	//Taste choice led
	output	reg				Taste_led		,
	//slot
	output	reg				slot			,
	//sell enable
	output	reg				sell_en			,
	//sell out
	output	wire	[3:0]	sell_out		,
	//return coin
	output	reg		[1:0]	Coin_10_re		,
	output	reg		[1:0]	Coin_5_re		

);

//========================================================================\
// =========== Define Parameter and Internal signals =========== 
//========================================================================/
localparam		IDLE	= 4'b0000	;
localparam		SALE	= 4'b0001	;
localparam		DONE	= 4'b0010	;
localparam		CHANGE	= 4'b0100	;
localparam		RETURN	= 4'b1000	;

reg			[3:0]		state		;
reg 		[4:0]		coin_cnt	;
reg			[3:0]		Taste_reg	;
reg 					change_end	;
reg 					return_end	;
//=============================================================================
//****************************     Main Code    *******************************
//=============================================================================
//状态机
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		state <= IDLE;
	else if(state == IDLE & coin_cnt >= 5'd15)	
		state <= SALE;
	else if (state == SALE & Taste_key !=4'd0)
	    state <=  DONE;
	else if (state == DONE & coin_cnt > 5'd15)
	    state <= CHANGE;
	else if (state == SALE & Cancel_key == 1'b1)
		state <= RETURN;
	else if ((state == CHANGE & change_end == 1'b1) | (state == RETURN & return_end == 1'b1) | sell_en == 1 | return_end == 1)
	    state <= IDLE;                   
	else
		state <= state;  
end

//输入硬币计数
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		coin_cnt <= 5'd0;
	else if (sell_en == 1 | return_end == 1)
	    coin_cnt <= 5'd0;    
	else if (coin_cnt < 20) begin
		if (Coin_10 == 1'b1)
		 	coin_cnt <= coin_cnt + 5'd10;	        
		else if (Coin_5 == 1'b1)
		 	coin_cnt <= coin_cnt + 5'd5; 
		else 
			coin_cnt <= coin_cnt;
	end

	else
		coin_cnt <= coin_cnt;	        
end

//口味显示灯控制和投币口控制
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0) begin
		Taste_led <= 1'b0;
		slot <= 1'b1;		
	end

	else if (state == SALE) begin
		Taste_led <= 1'b1;
		slot <= 1'b0;
	end
	else if (state == DONE) begin
		Taste_led <= 1'b0;
		slot <= 1'b1;
	end
	else begin
		Taste_led <= Taste_led;
		slot <= slot;
	end      
end

//出货使能
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		sell_en	 <= 1'd0;
	else if (state == DONE)
		sell_en	 <= 1'b1;		   
	else if (state == IDLE)
	    sell_en	 <= 1'b0;    
	else	
        sell_en <= sell_en;
end

//获取口味咖啡
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		Taste_reg <= 4'd0;
	else if(state == SALE)
		Taste_reg <= Taste_key;
	else if (state == IDLE)
	    Taste_reg <= 4'd0;
	else
	    Taste_reg <= Taste_reg;    	     
end

assign  sell_out = sell_en ? Taste_reg : 4'd0;

//退币
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0) begin
		Coin_10_re	<= 2'd0;
		Coin_5_re	<= 2'd0;
		change_end	<= 1'b0;
		return_end	<= 1'b0;	
	end
	else if(state == RETURN)begin
		if (coin_cnt == 5'd20) begin	        
			Coin_10_re	<= 2'd2;
			Coin_5_re	<= 2'd0;
		end
		else if(coin_cnt == 5'd15)begin
			Coin_10_re	<= 2'd1;
			Coin_5_re	<= 2'd1;			
		end
		else begin
			Coin_10_re	<= Coin_10_re;
			Coin_5_re	<= Coin_5_re;				
		end
		return_end	<= 1'b1;					
	end
	else if (state == CHANGE) begin
			Coin_10_re	<= 2'd0;
			Coin_5_re	<= 2'd1;
			change_end	<= 1'b1;		
	end      
	else begin
		Coin_10_re <= 2'd0;
		Coin_5_re <= 2'd0;
		change_end	<= 1'b0;
		return_end	<= 1'b0;
	end	     
end

endmodule

3.测试平台

`timescale 1ns/1ns
module tb_sim();

reg				sclk		;
reg				s_rst_n		;
reg				Cancel_key	;
reg		[3:0]	Taste_key	;
reg				Coin_10 	;
reg				Coin_5 		;

wire			Taste_led	;
wire			slot 		;
wire			sell_en		;
wire	[3:0]	sell_out	;

wire	[1:0]	Coin_10_re	;		
wire	[1:0]	Coin_5_re	;		


initial begin
	sclk = 1;
	s_rst_n =0;
	Cancel_key =0;
	Taste_key =4'd0;
	Coin_10 =0;
	Coin_5 = 0;
	#100
	s_rst_n =1;

	#200				//投入1块 一个，5角 一个，确认购买
	Coin_10 = 1;
	#100
	Coin_10 = 0;
	#200
	Coin_5 =1;
	#100
	Coin_5 = 0;
	#200
	Taste_key = 4'd2;
	#100
	Taste_key = 4'd0;

	#200			//投入1块 2个，确认购买，找零
	Coin_10 = 1;
	#300
	Coin_10 = 0;
	#200
	Taste_key = 4'd2;
	#100
	Taste_key = 4'd0;

	#200			//投入1块 2个，取消退钱
	Coin_10 = 1;	
	#300
	Coin_10 = 0;
	#100
	Cancel_key =1;
	#100
	Cancel_key =0;

end

always #50 sclk = ~ sclk ;

auto_caffe_teller 	auto_caffe_teller_inst(
	//system signals
	.sclk					(sclk		), 
	.s_rst_n				(s_rst_n	),
	//Cancel key
	.Cancel_key				(Cancel_key	),
	//Taste choice key
	.Taste_key				(Taste_key 	),
	//Coin input
	.Coin_10				(Coin_10	),
	.Coin_5					(Coin_5		),
	//Taste choice led
	.Taste_led				(Taste_led	),
	//slot
	.slot					(slot 		),
	//sell enable
	.sell_en				(sell_en	),
	//sell out
	.sell_out				(sell_out	),
	//return coin
	.Coin_10_re				(Coin_10_re	),
	.Coin_5_re				(Coin_5_re	)

);
endmodule

4.仿真波形