转载自：https://blog.csdn.net/hemmingway/article/details/78048845
1.来自kakuyou
http://www.icarus.com/eda/verilog/
开源的verilog 编译器，包含模拟器和基本逻辑综合模块。
http://www.geocities.com/SiliconValley/Campus/3216/GTKWave/gtkwave-win32.html
windows版的gtk-wave，一个图形波形察看工具
http://embedded.eecs.berkeley.edu/research.htm
大名鼎鼎的伯克里电子设计部，业界巨头们的工具大部分都是建立在这个部
发布的各种工具的基础上。
2.来自Tony Hsu’s Technical View
原文：http://icguy.blogspot.com/2008/05/vmm.html
正当大家把注意力集中在新秀OVM身上、还在担心非开源的VMM如何应对挑战时，昨天Synopsys不声不响地推出了VMM方法学的标准库以及应用的源代码。类似于OVM的官方网站OVM World(http://www.ovmworld.org/)，同时发布的还有VMM开源网站http://www.vmmcentral.org/，VMM完整的实现都可以在该网站下载。
Synopsys提供的代码包括以下：
– VMM Standard Library
– VMM Register Abstraction Layer application
– VMM Reusable Environment Composition application
– VMM Memory Allocation Manager application
– VMM Hardware Abstraction Layer application
– VMM Data Stream Scoreboard application
– VMM Macro Library
这是个令人兴奋的消息！随着验证在IC设计中的重要性不断被重视，EDA们巨头们不断推出新的策略吸引潜在客户。从AVM开源到OVM开源再到 VMM的开源，我们看到的是一系列积极的举措，在不断地推进行业向前发展。不管怎么样，对客户而言，终归是好消息，你需要的是在选择使用哪种方法进行验证 工作学时停顿片刻，花点时间仔细考虑下。
既然VMM都接招了，OVM赶快行动吧！至少，也该把OVM的User Guide发出来给支持者一些“新鲜”吧！^_^
3.来自phixcoco
原文：http://blog.csdn.net/phixcoco/archive/2006/08/13/1057134.aspx
SourceForge上搜到的关于Verilog/SystemVerilog/SystemC的开源项目
A: Verilog相关：
·Eclipse Verilog editor
http://sourceforge.net/projects/veditor
http://icarus.com/eda/verilog/
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
·Icarus Verilog
http://sourceforge.net/projects/iverilog
Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2001 plus extensions.
·Source Navigator for Verilog
http://sourceforge.net/projects/snverilog
http://sources.redhat.com/sourcenav
Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Deion Language.
·Icarus Verilog Test Suite
http://sourceforge.net/projects/ivtest
Provides a GPL’d test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com.
·Vtracer
http://sourceforge.net/projects/vtracer
VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
·VeriWell Verilog Simulator
http://sourceforge.net/projects/veriwell
VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell is the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book
·PVSim Verilog Simulator
http://sourceforge.net/projects/pvsim
PVSim is a Verilog Simulator for Mac OS X that uses AlphaX editor’s Verilog mode and features a fast compile-simulate-display cycle.
·Verilog Construction Toolkit
http://sourceforge.net/projects/vct
The Verilog Construction Toolkit is a C++ library which provides the ability to read in, create and or modify verilog cell-based structural netlists.
·Verilog Netlist Viewer / Editor
http://sourceforge.net/projects/netedit
The purpose of this tool is creation of tcl/tk - based environment for convenient Verilog netlist viewing and editing. This tool will allow development of TCL s in order to make structural changes in verilog netlist.
·SystemC to Verilog RTL converter
http://sourceforge.net/projects/sysc2ver
sysc2ver - SystemC to Verilog RTL converter
·FPGA C Compiler
http://sourceforge.net/projects/fpgac
FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info on Home Page.
·vIDE
http://sourceforge.net/projects/vlogide
vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features.
·Covered
http://sourceforge.net/projects/covered
Covered is a Verilog code-coverage utility using VCD/LXT style dumpfiles and the design to generate line, toggle, combinational logic and FSM state/arc coverage reports. Covered also contains a built-in race condition checker and GUI report viewer.
·veri-indent
http://sourceforge.net/projects/veriindent
Veri-indent is a verilog source code Parser,Analyzer and Beautifier. (similar to c ‘indent’ , but more than that). Verilog source can be formatted and Symbol table, list of registers,wires,pli calls in source code can be extracted.
·Teal
http://sourceforge.net/projects/teal
TEAL - C++ multithreaded library to verfiy verilog designs
·Reed-Solomon Core Compiler
http://sourceforge.net/projects/rstk
RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.
·XSpiceHDL
http://sourceforge.net/projects/xspicehdl
XSpiceHDL, a mixed-mode XSpice-Verilog HDL co-simulation environment incorporating GUI schematic capture, modified XSpice3f5 based engine and TCP inter-process communications via CodeModel and VPI DLL, written in C++ using the wxWindows API.
B: SystemVerilog相关：(真是少得可怜)
·HDLObf
http://sourceforge.net/projects/hdlobf
HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog. Support will be added for VHDL/SystemC in future.
C: SystemC相关：
·Open SystemC Initiative (OSCI)
http://sourceforge.net/projects/systemc
The Open SystemC Initiative (OSCI) is a collaborative effort to support and advance SystemC as a de facto standard for system-level design. SystemC is an interoperable, C++ SoC/IP modeling platform for fast system-level design and verification
·FERMAT SystemC Parser
http://sourceforge.net/projects/systemcxml
FERMAT’s SystemC Parser using Doxygen and Xerces-C++ XML
·SCLive
http://sourceforge.net/projects/sclive
SCLive is a modular Linux-Live Distribution dedicated to the OSCI SystemC simulator and it’s associated libraries. The distribution provides a fully working environement including a simulator kernel, wavefom viewer, IDE, tutorials and more.
·GreenSocs
http://sourceforge.net/projects/greensocs
http://www.greensocs.com
To develop SystemC infrustructure, basic IP, patches and add on library code for eventual standerdization. The GreenSocs project is made up of a number of contributions (sub projects). Please visit www.greensocs.com for more information.
www.opencores.org是IC行业有名的开源网站，有空了再到那里去转转，说不定会有不少收获！
4.来自sprhawk
原文：http://blog.chinaunix.net/u2/68344/article_85158.html
gEDA是一个Unix/Linux下作电路设计的软件集合－－而非一个独立的程序
官方网站见：http://www.geda.seul.org/
取自：http://www.geda.seul.org/tools/index.html
gEDA/gaf软件包所带的工具 (gschem and friends):
gschem :原理图设计
gnetlist :网络表生成
gattrib :属性编辑器
symbols :符号库
utils :工具集
gsymcheck :符号检查
examples : 例子
docu……
开放的源代码( opencores)网址（VHDL 和 VERILOG) [很好的设计参考]
http://www.opencores.org/cvsweb.shtml/ 有许多有用的源代码，并且调试过
http://www.oanda.com/convert/classic?user=freeipcore&lang=en
http://www.altera.com.cn/support/examples/exm-index.html 设计范例
http://www.alse-fr.com/English/ips.html
http://www.eda.org/ 国际官方组织 (可以找到很多有用的东西
www.xilinx-china.com
www.aldec.com