RAM

RAM:Radom Access Memory 随机存取存储器

Unlike the computer's processing chips, which are based on combinational logic, the computer's memory logic requires a clock-based sequential logic.。

这是课程的原话,也就是说对于存储器首先要建立时钟的概念。最简单的元素是flip-flop,即out(t) = out(t-1),在课程里用的是DFF。

利用DFF就可以构建1-Bit Register,主要是加入了一个Load。其HDL实现有个点是,可以创建一个circle,并对默认元素dffout进行使用并赋值。

/**
 * 1-bit register:
 * If load[t] == 1 then out[t+1] = in[t]
 *                 else out does not change (out[t+1] = out[t])
 */

CHIP Bit {
    IN in, load;
    OUT out;

    PARTS:
    // Put your code here:
    Mux(a = dffout,b = in,sel = load,out = muxout);
    DFF(in = muxout,out =dffout,out = out);
}

创建了1-Bit Register就可以创建m-Bit Register,这里的m表示该寄存器的长度。

一个计算机可以有N个寄存器,那如果选择一个寄存器进行读写操作呢,这就用到了地址的概念。比如有8个寄存器,即RAM8,就可以利用3个字节的address[3]来选择寄存器,课程里强调,这里的赋值不是选择一个来赋值,而是全都赋值,但只有一个寄存器会被读入正确的值。其实现思路就是,先确认8个寄存器是否读入正确值,即定义8个load值loadA/.../loadH,这个可以用DMux8Way,然后依次用Register进行操作,如果涉及到输出,就再用Mux8Way16(假设m=16)就可以啦

/**
 * Memory of 8 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM8 {
    IN in[16], load, address[3];
    OUT out[16];

    PARTS:
    // Put your code here:
    
    DMux8Way(in=load, sel=address, a=loadA, b=loadB, c=loadC, d=loadD, e=loadE, f=loadF, g=loadG, h=loadH);

    Register(in = in,load = loadA,out = outA);
    Register(in = in,load = loadB,out = outB);
    Register(in = in,load = loadC,out = outC);
    Register(in = in,load = loadD,out = outD);
    Register(in = in,load = loadE,out = outE);
    Register(in = in,load = loadF,out = outF);
    Register(in = in,load = loadG,out = outG);
    Register(in = in,load = loadH,out = outH);
    Mux8Way16(a=outA, b=outB, c=outC, d=outD, e=outE, f=outF, g=outG, h=outH, sel = address,out = out);
}

如果是更多的寄存器数目,比如RAM64,其地址为address[6],就可以用地址为address[3]的RAM8来操作了

 

猜你喜欢

转载自www.cnblogs.com/fanmu/p/10666180.html
RAM