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Quartus II 的project是.qpf的
University Program VWF这是波形文件
1.与或门电路设计
①与门电路设计
library ieee; use ieee.std_logic_1164.all; entity lian is port( a,b:in std_logic; y:out std_logic ); end; architecture rel_1 of lian is begin y<= a and b; end;②或门电路设计
library ieee; use ieee.std_logic_1164.all; entity lian2 is port( a,b:in std_logic; y:out std_logic ); end; architecture rel_1 of lian2 is begin y<= a or b; end;2. 三八译码器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY m38 IS PORT(A2,A1,A0,S1,S2,S3:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY m38; ARCHITECTURE ONE OF m38 IS SIGNAL S: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN S<=A2&A1&A0&S1&S2&S3; WITH S SELECT Y<="11111110" WHEN "000100", "11111101" WHEN "001100", "11111011" WHEN "010100", "11110111" WHEN "011100", "11101111" WHEN "100100", "11011111" WHEN "101100", "10111111" WHEN "110100", "01111111" WHEN "111100", "11111111" WHEN OTHERS; END ARCHITECTURE ONE;3. 八三编码器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY m83 IS PORT( D:IN STD_LOGIC_VECTOR(0 TO 7); A:OUT STD_LOGIC_VECTOR(0 TO 2) ); END ; ARCHITECTURE XIANI OF m83 IS BEGIN PROCESS(D) BEGIN IF (D(7)='0')THEN A<="111"; ELSIF (D(6)='0')THEN A<="110"; ELSIF (D(5)='0')THEN A<="101"; ELSIF (D(4)='0')THEN A<="100"; ELSIF (D(3)='0')THEN A<="011"; ELSIF (D(2)='0')THEN A<="010"; ELSIF (D(1)='0')THEN A<="001"; ELSIF (D(0)='0')THEN A<="000"; ELSE A<="ZZZ"; END IF; END PROCESS; END;4.八选一数据选择器
library ieee; use ieee.std_logic_1164.all; entity elec is port(d0,d1,d2,d3,d4,d5,d6,d7,a0,a1,a2,s:in std_logic; y:out std_logic); end elec; architecture hxx of elec is signal a:std_logic_vector (2 downto 0); begin process (a0,a1,a2) begin a<=a2&a1&a0; if(s='0') then case a is when"000"=>y<=d0; when"001"=>y<=d1; when"010"=>y<=d2; when"011"=>y<=d3; when"100"=>y<=d4; when"101"=>y<=d5; when"110"=>y<=d6; when others=>y<=d7; end case; end if; end process; end hxx;5.四位二进制数值比较器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY comp IS PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); YA,YB,YC: OUT STD_LOGIC); END comp; ARCHITECTURE behave OF comp IS BEGIN PROCESS (A,B) BEGIN IF (A > B) THEN YA <='1'; YB <='0'; YC <='0'; ELSIF(A < B) THEN YA <='0'; YB <='1'; YC <='0'; ELSE YA <='0'; YB <='0'; YC <='1'; END IF; END PROCESS; END behave;6.全加器
library ieee; use ieee.std_logic_1164.all; entity fulladd is port ( a,b,ci: in std_logic; s,co : out std_logic ); end entity; architecture rtl of fulladd is begin s <= a xor b xor ci; co <= (a and b) or (a and ci) or (b and ci); end rtl;7.半加器
Library ieee; Use ieee.std_logic_1164.all; Entity halfadd is Port(a,b:in std_logic; S,c:out std_logic); end halfadd; Architecture add of halfadd is begin S<=a xor b; c<=a and b; end;8.全减器
library ieee; use ieee.std_logic_1164.all; entity fullsub is port (xin,yin,sub_in:in std_logic; diffr,sub_out:out std_logic); end; architecture one of fullsub is component halfsub port (x,y:in std_logic; diff,s_out:out std_logic); end component; signal c,d,e:std_logic; begin u1:halfsub port map(x => xin,y => yin,diff => c,s_out => d); u2:halfsub port map(x => c,y => sub_in,diff => diffr,s_out => e); sub_out <= d or e; end;9.半减器
library ieee; use ieee.std_logic_1164.all; entity halfsub is port ( x,y:in std_logic; diff,s_out:out std_logic); end; architecture one of halfsub is begin process(x,y) begin diff <= x xor y; s_out <= (not x) and y; end process; end;10.触发器（D触发器）
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY cfq IS PORT ( clk, d: IN STD_LOGIC; q:OUT STD_LOGIC); END cfq; ARCHITECTURE rtl OF cfq IS BEGIN PROCESS(clk) BEGIN IF(clk' EVENT AND clk='1') THEN q<=d; END IF; END PROCESS; END rtl;11.计数器（同步复位加法计数器）
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity addcount is port( CLK,RST,EN: in std_logic; DOUT : out std_logic_vector (3 downto 0); COUT : OUT std_logic ); end addcount; architecture behav of addcount is begin process(CLK,RST,EN) variable Q : std_logic_vector (3 downto 0); begin if CLK 'event and CLK = '1' then if RST = '1' then Q := (others => '0'); else if EN = '1' then if Q < 9 then Q := Q + 1; else Q := (others => '0'); end if; end if; end if; end if; if Q = "1001" then COUT <= '1'; else COUT <= '0'; end if; DOUT <= Q; end process; end behav;12.寄存器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY jcq IS PORT(CLK,CO:IN STD_LOGIC; MD:IN STD_LOGIC_VECTOR(2 DOWNTO 0); D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); CN:OUT STD_LOGIC); END ENTITY; ARCHITECTURE BEHAV OF jcq IS SIGNAL REG:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CY:STD_LOGIC; BEGIN PROCESS(CLK,MD,CO) BEGIN IF CLK'EVENT AND CLK='1' THEN CASE MD IS WHEN "001" =>REG(0)<=CO; REG(7 DOWNTO 1)<=REG(6 DOWNTO 0); CY<=REG(7); WHEN "010"=>REG(0)<=REG(7); REG(7 DOWNTO 1)<=REG(6 DOWNTO 0); WHEN "011"=>REG(7)<=REG(0); REG(6 DOWNTO 0)<=REG(7 DOWNTO 1); WHEN "100"=>REG(7)<=CO; REG(6 DOWNTO 0)<=REG(7 DOWNTO 1); CY<=REG(0); WHEN "101"=>REG(7 DOWNTO 0)<=D(7 DOWNTO 0); WHEN OTHERS=>REG<=REG; CY<=CY; END CASE; END IF; END PROCESS; QB(7 DOWNTO 0)<=REG(7 DOWNTO 0); CN<=CY; END BEHAV;13.锁存器
LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY scq IS PORT (CLK,D : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END ; ARCHITECTURE BHV OF scq IS BEGIN PROCESS (CLK,D) BEGIN IF CLK ='1' THEN Q <=D ; END IF ; END PROCESS ; END BHV ;14.偶数分频器（n=4）
Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Use ieee.std_logic_arith.all; Entity osfpq is generic(N: integer:=4); port( clkin: IN std_logic; clkout: OUT std_logic ); End osfpq; Architecture a of osfpq is signal cnt: integer range 0 to n-1; Begin process(clkin) begin if(clkin'event and clkin='1') then if(cnt<n-1) then cnt <= cnt+1; else cnt <= 0; end if; end if; end process; process(cnt) begin if(cnt<n/2) then clkout <= '1'; else clkout <= '0'; end if; end process; End a;15.EDA程序设计（出租车计价器）
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity eeda is --定义实体[3] port ( clk_256 :in std_logic; --频率为256Hz的时钟 start :in std_logic; --计价使能信号 stop:in std_logic; --等待信号 fin:in std_logic; --公里脉冲信号 cha3,cha2,cha1,cha0:out std_logic_vector(3 downto 0); --费用数据 km1,km0:out std_logic_vector(3 downto 0); --公里数据 min1,min0: out std_logic_vector(3 downto 0)); --等待时间 end eeda; architecture behav of eeda is signal f_16,f16,f_1:std_logic; signal q_16:integer range 0 to 15; --分频器 signal q16:integer range 0 to 15; --分频器 signal q_1:integer range 0 to 255; --分频器 signal w:integer range 0 to 59; --秒计数器 signal c3,c2,c1,c0:std_logic_vector(3 downto 0); --制费用计数器 signal k1,k0:std_logic_vector(3 downto 0); --公里计数器 signal m1:std_logic_vector(2 downto 0); --分的十位计数器 signal m0:std_logic_vector(3 downto 0); --分的个位计数器 signal en1,en0,f:std_logic; --使能信号 begin fenpin:process(clk_256,start) --分频器模块 begin if clk_256'event and clk_256='1' then if start='0' then q_16<=0;q16<=0;f_16<='0';f16<='0';f_1<='0';f<='0'; else if q_16=15 then q_16<=0;f_16<='1'; --此if语句得到频率为16Hz的信号 else q_16<=q_16+1;f_16<='0'; end if; if q16=15 then q16<=0;f16<='1'; --此if语句得到另一个频率为16Hz的信号 else q16<=q16+1;f16<='0'; end if; if q_1=255 then q_1<=0;f_1<='1'; --此if语句得到频率为1Hz的信号 else q_1<=q_1+1;f_1<='0'; end if; if en1='1' then f<=f_16; --此if语句得到计费脉冲f elsif en0='1' then f<=f16; else f<='0'; end if; end if; end if; end process; process(f_1) --等待计时模块 begin if f_1'event and f_1='1' then if start='0' then w<=0;en1<='0';en0<='0';m1<="000";m0<="0000";k1<="0000";k0<="0000"; elsif stop='1' then --等待计时模块 if w=59 then w<=0; --此if语句完成等待计时 if m0="1001" then m0<="0000"; --此if语句完成分计数 if m1<="101" then m1<="000"; else m1<=m1+1; end if; else m0<=m0+1; end if; if m1&m0>"0000001"then en1<='1'; --此if语句得到en1使能信号 else en1<='0'; end if; else w<=w+1;en1<='0'; end if; elsif fin='1' then --计程模块 if k0="1001" then k0<="0000"; --此if语句完成公里脉冲计数 if k1="1001" then k1<="0000"; else k1<=k1+1; end if; else k0<=k0+1; end if; if k1&k0>"00000010" then en0<='1'; --此if语句得到en0使能信号 else en0<='0'; end if; else en1<='0';en0<='0'; end if; cha3<=c3;cha2<=c2;cha1<=c1;cha0<=c0; --费用数据输出 km1<=k1;km0<=k0;min1<='0'&m1;min0<=m0; --公里数据、分钟数据输出 end if; end process; process(f,start) --计费模块[2] begin if start='0' then c3<="0000";c2<="0001";c1<="0000";c0<="0000"; elsif f'event and f='1' then if c0="1001" then c0<="0000"; --此if语句完成对费用的计数 if c1="1001" then c1<="0000"; if c2="1001" then c2<="0000"; if c3<="1001" then c3<="0000"; else c3<=c3+1; end if; else c2<=c2+1; end if; else c1<=c1+1; end if; else c0<=c0+1; end if; end if; end process; end behav;