Xilinx ISE工程创建全流程笔记

注:可参考ISE-Help-Help Topics


Creating a Project

1.File-New Project-New Project Wizard

2.Create New Project — set the name, location, and project type

   top-level source type: HDL (VHDL或Verilog),Schematic(原理图),EDIF(网表),NGC/NGO(网表)

   ->Next

3.Project Settings — set the device and project properties

Evaluation Development Board: None Specified (指定官方开发板,手动设置即点None Specified)

Product Category: All (指定产品类别,可过滤下发的设备选项)

Family: Spartan6 (Xilinx FPGA芯片所属的系列)

Device: XC6SLX45 (Xilinx FPGA芯片的型号)

Package: CSG324 (Xilinx FPGA芯片的封装型号)

Speed: -2 (指定速度等级)

Top-level Souce Type: HDL (顶层设计的方式)

Synthesis Tool: XST (综合工具,可以安装并使用如Synplify等第三方工具)

Simulator: Modelsim-SE mixed (仿真工具,可以使用Xilinx自身的ISim工具或第三方的Modelsim或Questa)

Perfered Language: Verilog

Property Specification in Project File: Store all values (项目存储在.xise文件中的属性)

Manual Compile Order: 空 (可选是否手动修改编译顺序)

VHDL Source Analysis Standard: VHDL-93 (指定前段设计层次分析程序所使用的VHDL标准,可选VHDL-93或VHDL-200X,注XST不支持VHDL-200X,此时必须使用第三方的综合工具)

Enable Message Filtering: 空 (可选是否启用信息过滤)

4.Project Summary — review the information 项目摘要

   ->Finish

5.随即生成项目工程,并生成项目的.xise文件,注:随后仍可在工程的Design Properties中修改工程的各属性


Working with Project Source Filles

1.Project-New Source Wizard-Verilog Module

2.Select Source Type:

Source type: Verilog Module

File name: 以字母开头,并且只能包含字母、数字和下划线

Source File Types: 参见Command Line Tools User Guide (UG628)

Block RAM Memory Map (BMM File): .bmm (用于PowerPC或MicroBlaze,最多仅一个)

ChipScope Definition and Connection (CDC File): .cdc (用于ChipScope)

Electronic Data Interchange Format (EDIF): .edn, .edf, .edif, .sedif (网表)

ELF: .elf (可执行CPU代码映像)

Embedded Processor: .xmp (用XPS创建的微处理器项目文件)

Implementation Constraints File also known as User Constraints File (UCF): .ucf (管脚约束文件)

IP (Architecture Wizard): .xaw (配置体系结构功能或模块的预定义逻辑功能)

IP (CORE Generator): .xco (预定义的逻辑函数)

Memory Definition (MEM File): .mem (存储器文件,最多仅一个)

Schematic: .sch (原理图设计文件)

System Generator module: .sgp (数字信号处理dsp模块)

Verilog Module and Verilog Test Fixture: .v

VHDL Module, VHDL Package and VHDL Test Bench: .vhd

Xilinx Native Generic Database: .ngc, .ngo (Xilinx专有的一种网表文件)

  ->Next-Define Module-Next-Summary-Finish

3.Adding a Source File to a Project

  Project-Add Source-Open->Adding Source Files dialog box

Association: All (选择Design View,如没配置,直接选All)

Library: work

  ->OK

4.Adding a Copy of a Source File to a Project

Project-Add a Copy of Source->Adding Source Files dialog box

5.Editing a Source File

6.Removing Files from a Project


UCF File Constraints

1.File-New(Ctrl+n)-Text File-OK

添加引脚定义

针对普通IO口:

NET “端口名词” LOC = 引脚编号 | IOSTANDARD = "电压";

对于时钟端口,还可定义时钟周期约束。即先在时钟网线clk附加一个TNM_NET约束,把clk驱动的所有元件定义为一个sys_clk_pin的分组,再用TIMESPEC约束定义时钟周期

注:UCF文件对大小写敏感,但对文件中的NET不区分大小写

  ->Save-**.ucf

2.Project-Add Source

3.Generate Programming File(Double Cliek) 即编译,生成.bit文件


Modelsim仿真验证

1.Project-Design Properties

   Simulator:Modelsim-SE Mixed

2.切换为Simulation模式

点中Top文件-右键Simulate Behavioral Model-Process Properties

->Cimpiled Library Directory->填入编译库文件路径C:\Xilinx\Xilinx_lib-OK

3.Project-New Source-Verilog Test Fixture(即Testbench,测试脚本文件)

  ->Next-Finish

4.设计测试文件vtf**.v

  其下面为设计文件(Top文件),选中vtf**.v,双击Simulate Behavioral Model

注:Modelsim中,上双箭头Restart 下双箭头 Run All


FPGA下载、测试

1.To Configure or Program a Device

双击Configure Target Device-进入Implement模式

2.To Generate Related Configuration Files

iMPACT环境中-双击Boundary Scan 扫描JTAG链

3.右键Initialize Chain — 检测FPGA芯片

   ->Auto Assign Configuration Files Query Dialog-Yes-导入.bit文件(重新上电会丢失)

   ->Attach SPI or BPI PROM(是否进行Flash PROM的烧写)-No

   -右键FPGA芯片-Program->Program succeeded


MCS文件生成-MCS文件可存入Flash,重上电不会丢失

1.iMPACT环境中

   File-New Project-Yes->Welcome to iMPACT-Prepare a PROM File-OK

2.PROM File Formatter — 确定SPI Flash型号、容量、MCS文件名、放置目录

Step1.Select Storage Target: SPI Flash-Configure Single FPGA->

Step2.Add Storage Device: 128M-Add Storage Device->

Step3.Enter Data: Output File Name、Output File Location、

   Flash/PROM File Property-File Format: MCS

   -OK->Add Device窗口-添加.bit文件->Add Device-No

3.iMPACT Progresses界面

  双击Generate File-生成MCS文件->Generate Succeeded


MCS文件的Flash下载

1.双击Boundary Scan

2.右键-Initialize Chain

   ->Auto Assign Configuration Files Query Dialog-No(不配置.bit文件)-OK

   ->双击生成的图中的SPI/BPI-Open

   ->Select Attached SPI/BPI-Flash型号: W25Q128BV-OK

   选中Flash图标-右键-Program-

   ->Device Programming Properties-OK->Program Succeeded

猜你喜欢

转载自blog.csdn.net/Zenor_one/article/details/86002154