Vivado block design with both AXI GPIO and custom IP (ZEDBOARD)

In this article, I will introduce how to use custom IP to control LEDs on zedboard, and how to use AXI GPIO to control pmod on zedboard. (Pmod can read or write signal)

利用 custom ip来控制zedboard 上的led灯， 我的custom ip是一个自己写的程序， 3-8译码器， 用输出的8位信号来控制led灯。

利用 axi gpio 来控制gpio pmod的输入和输出，ja输出激励给面包板上的SN74LS138 译码器芯片， jb读取38译码器芯片的输出到sdk终端，比较两者结果。这是一个我简单的芯片验证练习。 这种方法可以用于普遍的芯片测试，以后我会放上我的能测试所有芯片的完整过程～～～～ 0 。0 ～～～～～

Block design in Vivado:

Description:

Custom Ip is 3-8 decoder verilog code, it will output the 8' bit results to control the leds on zedboard. 

AXI_GPIO will control GPIOs(Pmod) on zedboard to read or write signal. I output three signal to the SN74LS138 decoder on breadboard from PMOD JA, and read all eight output signals of SN74LS138 from Pmod JB. Compare those two results. This is a simple chip validation progress.

Part one - Custom IP: 

First step: Create a block design ->Tools -> Create and Package New IP -> Create new AXI4 Peripheral -> set a name for your new IP.(This IP will be saved under a file named "ip_repo" in your working directory) The default setting of the number of registers is 4, I'll leave it as 4 since I only need one register in my design. 

Choosing edit ip :

Paste your Verilog code to your IP design sources. 

After that, we can start to edit the top-level handshake file: 

1. In your <xxxip>.v file, add the new port of your custom IP (if you don't have input or output of your custom ip, you don't need to edit this file):

2. Edit your <xxxip>_S00_AXI.v file:

Declare the module of your custom Verilog code (I decided to use the first reg as my input trigger): 

/********************************************************

If you don't want to output your ip result to any GPIOs of your zedboard and only want to check the value in SDK terminal, you can use one of those 4 registers in your ip to save that value. For example, if you want to save the result to register2, you can replace the name of the second register with the name of your result (for example, replace"slv_reg1" with "dout") :

********************************************************/

Now we are done with the setting part, you can see the new hierarchy like this:

Update all changes and repack IP:

The IP window will close after repacking, you can edit this IP by right-clicking this IP in block design -> Edit in IP packager. Now you can find your IP in your IP library, add it to your block design.

Part two - AXI GPIO: 

Set the direction and width of your AXI GPIOS:

I have two AXI GPIOS, the first one the 3 bits-output, the second one is 8bits-input.

Add zynq IP, I only need one UART here:

Click automatic connection.

Don't forget to generate  "OUTPUT products"

Right-click your block design source and chose "output products -> global".

Right-click your block design source and chose "Create HDL Wrapper".

Add constraints:

Two ways 

You can either write a new constraint file:

Or set those pins one by one after synthesis:

Run synthesis -> open synthesis design ->Window ->I/O ports

Here, I use Pmod JA to output signals, JB to read signals, custom IP to control LEDS on zedboard.

You can find the pin map table on the user guide:

 (Remember, the JA1 is pin number 0. JA2 is pin number 1)

Save constraints file, generate the bitstream.

Now you have a bit file. You can export it to SDK:

File -> Export -> Export Hardware

File -> Launch SDK

Linux system control: SDK

Create a new application:(choose a template to begin)

"Hello world" or empty application.

// if there any error with the .h library, regenerate bsp. 

#include <stdio.h>
#include "xparameters.h"
#include"xil_io.h"
#include "xgpio.h"
#include "xil_printf.h"
# include "xbasic_types.h"
int main()
{	//decoder_ip
	//u32 adder_out;
    xil_printf("Starting decoder testing\n\r");
    //write 3 bit signal to my custom ip "my_decoder"
    Xil_Out32(XPAR_MYDECODER_0_S00_AXI_BASEADDR, 0x5);  //write value 0x5 to address XPAR_MYDECODER_0_S00_AXI_BASEADDR
    //you can find the value of base address XPAR_MYIP_0_S00_AXI_BASEADDR in "xparameter.h"
    ////////gpios
	 XGpio s_in, s_out;
	 int in_check;
	 xil_printf("\n -- Start of the Program --\r\n");
	//sig_out:output write sig to JA
	XGpio_Initialize(&s_out, XPAR_OUTPUT_SIG_DEVICE_ID);
	XGpio_SetDataDirection(&s_out, 1, 0x41200000);
        //sig_in:read sig from JB
	XGpio_Initialize(&s_in, XPAR_SIG_IN_DEVICE_ID);
	XGpio_SetDataDirection(&s_in, 1, 0x41210000);
	//logic:
	xil_printf("-- Output signal to pmod JA1 --\r\n");
	XGpio_DiscreteWrite(&s_out, 1,0x5);//output signal
	xil_printf("-- Read signal from pmod JB1 --\r\n");
	in_check = XGpio_DiscreteRead(&s_in, 1); //read signal
	xil_printf("The Decimal output of decoder chip is: %d\n\r", in_check);


    return 0;
}

Save -> connect zedboard -> programFPGA ->run on GDB/system debugger.

Since I write "0x5" to my custom ip "3-8" decoder, the 3 bit input is 101, the result of my custom ip is: 00000100, so led U22 will lit up:

According to the data sheet of decoder SN74LS138, the results that  read by pmod is: 11111011 -> 251 

Results in SDK terminal