一下内容来自：
en.DM00287603.pdf
AN4861 Application note
LCD-TFT display controller (LTDC) on STM32 MCUs
https://my.st.com/content/my_st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-discovery-kits/32f429idiscovery.html
Thanks to their embedded LCD-TFT display controller (LTDC), the STM32 MCUs allow to directly drive high-resolution display panels without any CPU intervention. In addition, the LTDC can access autonomously to internal memories or external memories to fetch pixel data.
autonomously 自主地；独立地；独立自主地
A basic embedded graphic system is composed of a microcontroller, a framebuffer, a display controller and a display glass
The microcontroller computes the image to be displayed in the framebuffer, assembling
graphical primitives such as icons or images. The CPU performs this operation by
running a graphical library software. This process can be accelerated by a dedicated
hardware like the DMA2D Chrom-Art Accelerator®, used by the graphical library. The
more often the framebuffer is updated, the more fluent the animations are (animation
fps).
graphical primitives ：图元
The framebuffer is a volatile memory used to store pixel data of the image to be
displayed. This memory is usually called the graphic RAM (GRAM). The required size
of the framebuffer depends on the resolution and color depth of the display. See
Section 4.2.1: Framebuffer memory size requirements and location for more
information on the required size of the framebuffer.
– Double buffering is a technique which uses double framebuffers to avoid
displaying what is being written to the framebuffer.
volatile：易变的；无定性的；无常性的；可能急剧波动的
• The display controller is continuously “refreshing” the display, transferring the
framebuffer content to the display glass 60 times per second (60 Hz). The display
controller can be embedded either in the display module or in the MCU.
• The display glass is driven by the display controller and is the responsible to display the
image (which is composed of a matrix of pixels).
A display is characterized by:
– Display size (resolution): is defined by the number of pixels of the display which is
represented by horizontal (pixels number) x vertical (lines number).
– Color depth: defines the number of colors in which a pixel can be drawn. It is
represented in bits per pixel (bpp). For a color depth of 24 bpp (which can also be
represented by RGB888) a pixel can be represented in 16777216 colors.
– Refresh rate (in Hz): is the number of times per second that the display panel is
refreshed. A display shall be refreshed 60 times per seconds (60 Hz) since lower
refresh rate creates bad visual effects.
Display module categories 显示模块分类
也即是液晶模块分类
categories 分类；产品分类；种类
The display modules are classified in two main categories, depending on whether they embed or not an internal controller and a GRAM.
• The first category corresponds to the displays with an on-glass display controller and a
GRAM (see Figure 2).
• The second category corresponds to the displays with an on-glass display with no main
controller and that have only a low-level timing controller.
To interface with displays without controller nor GRAM the used framebuffer may be
located in the MCU’s internal SRAM (see Figure 3) or located in an external memory
(see Figure 4).
显示工艺
There are many display technologies available on the market, the two main technologies used are described below:
• LCD-TFT displays (liquid crystal display - thin film transistor): is a variant of LCD that
uses the TFT technology to improve the control of each pixel. Thanks to the TFT
technology, each pixel can be controlled by a transistor, allowing a fast response time
and an accurate color control.
• OLED displays (organic LED): the pixels are made of organic LEDs emitting directly the
light, offering a better contrast and an optimized consumption. The OLED technology
enables the possibility to use flexible displays, as no glass nor backlight are required.
The response time is very fast and the viewing angle is free as it does not depend on
any light polarization.
The way of driving the display module is quite similar in TFT and OLED technologies, the main difference is in the backlight requirement, as the OLED is not requiring any.
显示接口标准
MIPI display bus interface (MIPI-DBI)
The MIPI-DBI is one of the first display standards published by the MIPI Alliance to specify the display interfaces. The three types of interfaces defined inside the MIPI-DBI are:
• Type A: based on Motorola 6800 bus
• Type B: based on Intel® 8080 bus
• Type C: based on SPI protocol
The MIPI-DBI is used to interface with a display with an integrated graphic RAM (GRAM). The pixel data is updated in the local GRAM of the display. Figure 5 illustrates a MIPI-DBI type A or B display interfacing example.
MIPI display parallel interface (MIPI-DPI)
The DPI standardizes the interface through a TFT controller. An example is when using a 16 to 24-bit RGB signaling in conjunction with synchronization signals (HSYNC, VSYNC, EN and LCD_CLK).
The DPI is used to interface with a display without a framebuffer. The pixel data must be streamed real time to the display.
The real-time performance is excellent, but it requires a high bandwidth in the MCU to feed the display.
LCD-TFT display controller on STM32 MCUs
The LTDC on the STM32 microcontrollers is an on-chip LCD display controller that provides up to 24-bit parallel digital RGB signals to interface with various display panels. The LTDC can also drive other display technologies with parallel RGB interface like the AMOLED displays. The LTDC allows interfacing with low-cost display panels which do not embed neither a controller nor a graphic RAM.
portfolio — 系列产品，组合
LTDC in a smart architecture
The LTDC is a master on the AHB architecture which performs read access on internal and external memories. The LTDC has two independent layers, each one with its own FIFO enabling more flexibility of the display.
The LTDC controller autonomously fetches graphical data at the speed of the AHB bus from the framebuffer. The graphical data is then stored in one of the FIFO internal layers then driven to the display.
The system architecture enables that graphics can be built and plotted to the screen without any CPU intervention. The LTDC retrieves the data belonging to an image from the framebuffer, while the Chrom-Art Accelerator® (DMA2D) is preparing the next images.
The LTDC interface is integrated in a smart architecture allowing:
• LTDC autonomously fetches the graphical data from the framebuffer (can be internal
memories such as internal Flash, internal SRAM or external memories such as
FMC_SDRAM or Quad-SPI) and drives it to the display.
• DMA2D as an AHB master can be used to offload the CPU from graphics intensive
tasks.
• LTDC is able to continue displaying graphics even in sleep mode when the CPU is not
running.
• The multi-layer AHB bus architecture improves memories throughput and leads to
higher performance.
System architecture on STM32F429/439 and STM32F469/479 microcontrollers
The system architecture of the STM32F429/439 line and the STM32F469/479 line consists mainly of 32-bit multilayer AHB bus matrix that interconnects ten masters and nine slaves (eight slaves for the STM32F429/F439). The LTDC is one of the ten AHB masters on the AHB busmatrix.
The LTDC can autonomously access all the memory slaves on the AHB bus matrix, such as FLASH, SRAM1, SRAM2, SRAM3 FMC or Quad-SPI enabling an efficient data transfer which is ideal for graphical applications. Figure 9 shows the LTDC interconnection in the STM32F429/439 and STM32F469/479 lines systems.
Advantages of using an STM32 LTDC controller
Table 4 summarizes the major advantages of using the STM32’s embedded LTDC interface.
FMC
FMC用于操作SDRAM，通过不断刷新SDRAM保证数据的正确性
LCD-TFT (LTDC) display controller description
The LTDC is a controller that reads the data of images in a line per line fashion
读数据是一行一行的读
On every pixel clock-raising edge or clock-falling edge and within the screen active area, the LTDC layer retrieves one pixel data from its FIFO, converts it to the internal ARGB8888 pixel format and blends it with the background and / or with the other layer pixel color. The resulting pixel, coded in the RGB888 format, goes through the dithering unit and is driven into the RGB interface. The pixel is then displayed on the screen.
blend混合,搀合,混杂,掺杂
LTDC clock domains
The LCD-TFT controller peripheral uses three clock domains:
• AHB clock domain (HCLK): used to transfer data from the memories to the FIFO layer
and the other way around.
• APB clock domain (PCLK): used to access the configuration and status registers.
• The pixel clock domain (LCD_CLK): used to generate the LCD-TFT interface signals.
The LCD_CLK output should be configured following the panel requirements through
the PLL.
LCD-TFT pins and signal interface
To drive LCD-TFT displays, the LTDC provides up to 28 signals using simple 3.3 V signaling including:
• Pixel clock LCD_CLK.
• Data enable LCD_DE.
• Synchronization signals (LCD_HSYNC and LCD_VSYNC).
• Pixel data RGB888.
The LTDC controller may support other display technologies if their interface is compatible.
The LTDC interface output signals are illustrated in Table 6.
Other signals
It is usual that display panel interfaces include other signals that are not part of the LTDC signals described in Table 5. These additional signals are required for a display module to be fully functional. The LTDC controller is able to drive only signals described in Table 5.
The signals that are not part of the LTDC may be managed using GPIOs and other peripherals and may need specific circuits.
The display panels usually embed a backlight unit which requires an additional backlight control circuit and a GPIO.
Some display panels need a reset signal and also a serial interface such as I2C or SPI.
These interfaces are used in general for the display initialization commands or for the touch panel control.
Figure 12 shows a display panel connected to an STM32 MCU using the LTDC interface signals illustrated in Table 5.
The LTDC can output data according to the following parallel formats: RGB565, RGB666 and RGB888. So a 16-bit RGB565, 18-bit RGB888 or a 24-bit RGB888 display can be connected.
The LTDC control signals polarity is programmable allowing the STM32 microcontroller to drive any RGB parallel display. The control signals (Hsync, Vsync and data enable DE) as well as the pixel clock (LCD_CLK) can be defined to be active high or active low through the LTDC_GCR register.
Example of a typical LTDC display frame
The Figure 13 shows an example of a typical LTDC display frame showing the timing parameters described in Table 6.
