全加器(行为描述)

//半加器
module cy4(input A,B,Ci,
           output reg Co,S); 
always @(*)
begin
case({A,B,Ci})
3'b000: begin S = 0;Co = 0;end
3'b001: begin S = 1;Co = 0;end
3'b010: begin S = 1;Co = 0;end
3'b011: begin S = 0;Co = 1;end
3'b100: begin S = 1;Co = 0;end
3'b101: begin S = 0;Co = 1;end
3'b110: begin S = 0;Co = 1;end
3'b111: begin S = 1;Co = 1;end
default:;
endcase
end
endmodule