从一个reset fe(frame engine)函数看MTK7628XN寄存器的配置
函数实现如下：
void fe_reset(void)
{
\#if defined (CONFIG_RALINK_RT6855A)
/* FIXME */
\#else
u32 val;
val = sysRegRead(RSTCTRL);
printk("%s %d: Read register from 0x%x, value = 0x%x.\n", __FUNCTION__, __LINE__, RSTCTRL, val);
// RT5350 need to reset ESW and FE at the same to avoid PDMA panic //
\#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
val = val | RALINK_FE_RST | RALINK_ESW_RST ;
printk("%s %d: RALINK_FE_RST = 0x%x, RALINK_ESW_RST = 0x%x.\n", __FUNCTION__, __LINE__, RALINK_FE_RST, RALINK_ESW_RST);
\#else
val = val | RALINK_FE_RST;
\#endif
printk("%s %d: Write register 0x%x, value = 0x%x.\n", __FUNCTION__, __LINE__, RSTCTRL, val);
sysRegWrite(RSTCTRL, val);
\#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7628)
val = val & ~(RALINK_FE_RST | RALINK_ESW_RST);
\#else
val = val & ~(RALINK_FE_RST);
\#endif
printk("%s %d: Write register 0x%x, value = 0x%x.\n", __FUNCTION__, __LINE__, RSTCTRL, val);
sysRegWrite(RSTCTRL, val);
printk("%s %d: OK, return.\n", __FUNCTION__, __LINE__);
\#endif
}
编译后，运行，串口打印输出：
Reset frame engine!
fe_reset 2199: Read register from 0xb0000034, value = 0x6400000.
fe_reset 2203: RALINK_FE_RST = 0x200000, RALINK_ESW_RST = 0x800000.
fe_reset 2207: Write register 0xb0000034, value = 0x6e00000.
fe_reset 2214: Write register 0xb0000034, value = 0x6400000.
fe_reset 2216: OK, return.
从打印输出中可以看到寄存器地址是0xb0000034，寄存器的初始值是0x6400000;
然后设置寄存器的FE_RST标志位和ESW_RST标志位，分别是0x200000和0x800000；这两个数值在文件.\linux-2.6.36.x\arch\mips\include\asm\mach-ralink\rt_mmap.h中定义，如下（CONFIG_RALINK_MT7628是被定义的）：
#define RALINK_SYSCTL_BASE 0xB0000000
#define RALINK_TIMER_BASE 0xB0000100
#define RALINK_INTCL_BASE 0xB0000200
#define RALINK_MEMCTRL_BASE 0xB0000300
#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
#define RALINK_MIPS_CNT_BASE 0x10000500
#define RALINK_PIO_BASE 0xB0000600
#define RALINK_SPI_SLAVE_BASE 0xB0000700
#define RALINK_I2C_BASE 0xB0000900
#define RALINK_I2S_BASE 0xB0000A00
#define RALINK_SPI_BASE 0xB0000B00
#define RALINK_UART_LITE1_BASE 0x10000C00
#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
#define RALINK_UART_LITE2_BASE 0x10000D00
#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
#define RALINK_UART_LITE3_BASE 0x10000E00
#define RALINK_PCM_BASE 0xB0002000
#define RALINK_GDMA_BASE 0xB0002800
#define RALINK_AES_ENGINE_BASE 0xB0004000
#define RALINK_FRAME_ENGINE_BASE 0xB0100000
#define RALINK_PPE_BASE 0xB0100C00
#define RALINK_ETH_SW_BASE 0xB0110000
#define RALINK_USB_DEV_BASE 0xB0120000
#define RALINK_MSDC_BASE 0xB0130000
#define RALINK_PCI_BASE 0xB0140000
#define RALINK_11N_MAC_BASE 0xB0180000
#define RALINK_USB_HOST_BASE 0x101C0000
#define RALINK_MCNT_CFG 0xB0000500
#define RALINK_COMPARE 0xB0000504
#define RALINK_COUNT 0xB0000508
//Interrupt Controller
#define RALINK_INTCTL_SYSCTL (1<<0)
#define RALINK_INTCTL_TIMER0 (1<<1)
#define RALINK_INTCTL_WDTIMER (1<<2)
#define RALINK_INTCTL_ILL_ACCESS (1<<3)
#define RALINK_INTCTL_PCM (1<<4)
#define RALINK_INTCTL_UART (1<<5)
#define RALINK_INTCTL_PIO (1<<6)
#define RALINK_INTCTL_DMA (1<<7)
#define RALINK_INTCTL_PC (1<<9)
#define RALINK_INTCTL_I2S (1<<10)
#define RALINK_INTCTL_SPI (1<<11)
#define RALINK_INTCTL_UARTLITE (1<<12)
#define RALINK_INTCTL_CRYPTO (1<<13)
#define RALINK_INTCTL_ESW (1<<17)
#define RALINK_INTCTL_UHST (1<<18)
#define RALINK_INTCTL_UDEV (1<<19)
#define RALINK_INTCTL_GLOBAL (1<<31)
//Reset Control Register
#define RALINK_SYS_RST (1<<0)
#define RALINK_TIMER_RST (1<<8)
#define RALINK_INTC_RST (1<<9)
#define RALINK_MC_RST (1<<10)
#define RALINK_PCM_RST (1<<11)
#define RALINK_UART_RST (1<<12)
#define RALINK_PIO_RST (1<<13)
#define RALINK_DMA_RST (1<<14)
#define RALINK_I2C_RST (1<<16)
#define RALINK_I2S_RST (1<<17)
#define RALINK_SPI_RST (1<<18)
#define RALINK_UARTL_RST (1<<19)
#define RALINK_FE_RST (1<<21)
#define RALINK_UHST_RST (1<<22)
#define RALINK_ESW_RST (1<<23)
#define RALINK_EPHY_RST (1<<24)
#define RALINK_UDEV_RST (1<<25)
#define RALINK_PCIE0_RST (1<<26)
#define RALINK_PCIE1_RST (1<<27)
#define RALINK_MIPS_CNT_RST (1<<28)
#define RALINK_CRYPTO_RST (1<<29)
//Clock Conf Register
#define RALINK_UPHY0_CLK_EN (1<<25)
#define RALINK_UPHY1_CLK_EN (1<<22)
#define RALINK_PCIE0_CLK_EN (1<<26)
#define RALINK_PCIE1_CLK_EN (1<<27)
//CPU PLL CFG Register
#define CPLL_SW_CONFIG (0x1UL << 31)
#define CPLL_MULT_RATIO_SHIFT 16
#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
#define CPLL_DIV_RATIO_SHIFT 10
#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
#define BASE_CLOCK 40 /* Mhz */
//AGPIO
#define MT7628_P0_EPHY_AIO_EN (0x1<<16)
#define MT7628_P1_EPHY_AIO_EN (0x1<<17)
#define MT7628_P2_EPHY_AIO_EN (0x1<<18)
#define MT7628_P3_EPHY_AIO_EN (0x1<<19)
#define MT7628_P4_EPHY_AIO_EN (0x1<<20)
`
在datasheet中查看Reset Control Register这个寄存器，该寄存器的地址是0x10000034，地址空间：0x10000000~0x100000ff这段(256Kbyte)都是用于sysctl。而该cpu是属于mips架构，该寄存器地址映射到内存的uncached和unmapped段，既是0xA000 0000开始的512Kbyte，所以在驱动代码中可以看到读写寄存器的内存映射地址是0xB000 0000 + offset地址，比如0xB0000034对应的就是0x1000 0034这个寄存器地址。