使用verilog实现流水灯

下面是使用 Verilog 实现流水灯的简单示例代码：

module TrafficLight(input clk, input reset, output reg green, output red);

reg [26:0] counter;

always @(posedge clk)
begin
    if (reset)
        counter <= 0;
    else
        counter <= counter + 1;
end

always @(posedge clk)
begin
    if (counter < 13'b1000_0000