1、使用时序逻辑对一个单比特信号进行毛刺滤除,高电平或者低电平宽度小于4个认为是毛刺
module filter(
input clk,
input rst_n,
input data_in,
output reg data_out
);
reg [1:0] cnt;
wire data_edge;
reg data_in_r;
//产生跳边沿指示信号
always@( posedge clk or negedge rst_n)
begin
if(!rst_n)
data_in_r<=1’b0;
else
data_in_r<=data_in;
end
assign data_edge=~data_in&&data_in_r;
//跳边沿来临后计数
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
cnt<=2'd0;
end
else if(data_edge)
begin
cnt<=2'd0;
end
else
begin
cnt<=cnt+1'b1;
end
//计数到3表示持续时间大于4个时钟周期,不是毛刺
always@(posedge clk or negedge rst_n)
if(!rst_n)
data_out<=1'b0;
else if(&cnt)
begin
data_out<=data_in_r;
end
endmodule