verilog求阶乘

求阶乘

`include "function.v"

`timescale 1ns/100ps

`define clk_cycle 50

 

module tryfuctTop;

 

reg[3:0] n,i;

reg reset,clk;

 

wire[31:0] result;

 

initial

  begin

    n=0;

    reset=1;

    clk=0;

    #100 reset=0;

    #100 reset=1;

    for(i=0;i<=15;i=i+1)

      begin

        #200n=i;

      end

    #100 $stop;

  end

 

always #`clk_cycle clk=~clk; 

  tryfuncttryfunct(.clk(clk),.n(n),.result(result),.reset(reset) );

 

endmodule

 

 

测试程序

module taskk;

  reg [31:0]fact;

 

  reg [3:0]b=4;

  //reg i;

  initial

  begin

   jiecheng(fact,b);

 end

task jiecheng;

  output [31:0]jc;

  integer  i;

  reg[31:0]wocao;

 input [3:0]a;

  begin

    //#10

    wocao=1;

    for (i=1;i<a;i=i+1)

    begin

   #10

    wocao=wocao*i;

   

    end

   

    jc=wocao;

  end

  endtask

 

endmodule

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转载自blog.csdn.net/kebu12345678/article/details/80585189
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