数字IC设计学习笔记_序列检测

数字IC设计学习笔记

6. 序列检测

1. 设计思想
2. Verilog 代码
3. Modelsim仿真

• 检测序列“Hello”

1 设计思想

1. 数据流输入等待“H”，如果检测到“H”，进入状态2;否则一直等待“H“
2. 检测当前字符是否为“e”，如果为“e”,进入状态3，否则返回1；
3. 检测当前字符是否为“l”，如果是，进入状态4；否则返回状态1；
4. 检测当前字符是否为“l”，如果是，进入状态5；否则返回状态1；
5. 检测当前字符是否为“o”，如果是，驱动led控制引脚，状态翻转，回到状态1，等待下一个“H”；否则返回状态1；

2 Verilog 代码

module fsm_hello#(//one hot code
	parameter CH_H = 5'b00001,//00001 
	parameter CH_e = 5'b00010,//00010
	parameter CH_l1 = 5'b00100,//00100
	parameter CH_l2 = 5'b01000,//01000
	parameter CH_o = 5'b10000 //10000

)
(
	input clk, //50M
	input rst_n,
	input [7:0] data, //ASCII code
	
	output reg led
);
	reg [4:0] state;

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			led <= 1'b1;
			state <= CH_H;
			end else begin
				case(state)
					CH_H:
						if(data == "H")begin
							state <= CH_e;
							led <= led;
						end else begin
							state <= CH_H;
							led <= led;
							end
					CH_e:
						if(data == "e")begin
							state <= CH_l1;
							led <= led;
						end else begin
							state <= CH_H;
							led <= led;
							end
					CH_l1:
						if(data == "l")begin
							state <= CH_l2;
							led <= led;
						end else begin
							state <= CH_H;
							led <= led;
							end
					CH_l2:
						if(data == "l")begin
							state <= CH_o;
							led <= led;
						end else begin
							state <= CH_H;
							led <= led;
						end	
					CH_o:
						if(data == "o")begin
							state <= CH_H;
							led <= ~led;
						end else begin
							state <= CH_H;	
							led <= led;
							end
						default: begin
							state <= CH_H;
							led <= led;
						end
				endcase
				
			end
	end

endmodule

`timescale 1ns/1ns
`define clock_period 20

module tb_fsm_hello;
	reg clk;
	reg rst_n;
	reg [7:0] ascii;
	wire led;
	
	fsm_hello uut(
		.clk(clk),
		.rst_n(rst_n),
		.data(ascii),
		.led(led)
	);
	
	initial clk = 1;
	always #(`clock_period/2) clk = ~clk;
	
	initial begin
		rst_n = 0;
		ascii = 0;
		#(`clock_period*200);
		rst_n = 1;
		#(`clock_period*200+1);
		forever begin
			ascii = "I";
		#(`clock_period);
			ascii = "A";
		#(`clock_period);
			ascii = "M";
		#(`clock_period);
			ascii = "Y";
		#(`clock_period);
			ascii = "H";
		#(`clock_period);
			ascii = "M";
		#(`clock_period);
			ascii = "n";
		#(`clock_period);
			ascii = "A";
		#(`clock_period);
			ascii = "H";
		#(`clock_period);
			ascii = "e";
		#(`clock_period);
			ascii = "l";
		#(`clock_period);
			ascii = "l";
		#(`clock_period);
			ascii = "o";
		#(`clock_period);
			ascii = "A";
		#(`clock_period);
			ascii = "M";
		#(`clock_period);
			ascii = "X";
		#(`clock_period);
			ascii = "A";
		#(`clock_period);
			ascii = "M";
		#(`clock_period);
			ascii = "X";
		#(`clock_period);		
		
		end
		
		
	end

endmodule

2. Modelsim仿真

【注】：个人学习笔记，如有错误，望不吝赐教，这厢有礼了~~~