Earlier, the methodology was to set false paths between the clock domAIns. This can cause re-convergence issues if two functionally-related signals are crossing from one domain to another domain. In a highly congested asic, the backend tools could do scenic routing if there are no constraints on the clock-crossing signals (false path) causing functional failures.
The following synthesis methodology is required for achieving successful functional operation of the
controller:
1.Do not set false path between the clock domains. Setting false paths between the clock domains cause scenic routing.
Example: set_false_path -from bus_clk -to mac_clk. This is not recommended.
2. Set max_delay constraint between the clock domains. This avoids scenic routing. The max_delay
should match the maximum allowed skew between two related signals by design and also the
maximum delays used in the re-convergence simulation.
异步FIFO如何认为两个模块是相邻的，通过设置set_max_delay来约束。可设最大时延为2个cycle。FIFO指针set_max_delay主要是用来约束skew。
set_false_path是unconstrained默认无约束的，可能会造成detour routing，即布线时path比较绕。set_max_delay用来约束跨时钟域时path的delay。
