[SV]SystemVerilog參數化的類（Parameterized Classes）

                               Parameterized Classes

       Parameterized classes are same as the parameterized modules in the verilog. parameters are like constants local to that particular class.

       The parameter value can be used to define a set of attributes in class. default values can be overridden by passing a new set of parameters during instantiation. this is called parameter overriding.

一、參數化的類

1、Class聲明

//---- class ----
class packet #(parameter int ADDR_WIDTH = 32,DATA_WIDTH = 32);
  bit [ADDR_WIDTH-1:0] address;
  bit [DATA_WIDTH-1:0] data   ;
 
  function new();
    address = 10;
    data    = 20;
  endfunction
endclass

2、Class例化：

packet  pkt;    //–>  creates pkt handle with default ADDR_WIDTH and DATA_WIDTH values.
//The default parameter value can be overridden when the class is instantiated.

packet #(32,64) pkt;  //–> creates pkt handle with ADDR_WIDTH = 32 and DATA_WIDTH = 64.

 

二、Pass a data type to a class

1、Class聲明

class packet #(parameter type T = int);
  T address;
  T data   ;
 
  function new();
    address = 10;
    data    = 20;
  endfunction
endclass

2、Class例化

packet pkt;                              // –>    address and data type is int
packet #(bit [31:0]) pkt;                // –>    address and data type is bit [31:0]