Abstract: VMM is a Sys-based te authentication method mVerilog language of science, by introducing it asserts, abstraction, automation and reuse of these four mechanisms to improve the validation of the project productivity. This paper describes an example of how to use VMM to establish a transaction-based reusable hierarchical verification platform.
0 Preface:
With the integrated circuit advent of deep sub-micron era, IC scale continues to expand, promote system-on- chip SoC (Systems- ON -A- Chip) development and application. Usually a scale SoC chip is about one million to several tens of millions of doors, the face of such a high degree of complexity, SoC design verification has become one of the topics most difficult and most challenging. VMM (Verification Methodology Manual) verification methodology using SystemVerilog language, introduced assertion, abstraction, automation and reuse mechanism to guide the verification engineer to build transaction-based reusable hierarchical verification platform, we can easily achieve directional testing , random testing data from checking, and reduce the complexity of test cases, improve verification productivity, reducing the total amount of verification code, shortening the time to market the product.
1 transaction-based verification
Transaction-based verification is a major validation techniques currently used. In simple terms the transaction is the interface to operate on. Transaction can be abstract and high-level, e.g. reliably transmitted a TCP packet, or may be a physical layer surface, such as in the APB write cycle on the connection. Transaction-based verification so that users do not have the underlying attention to detail, to verify a higher level of abstraction at the transaction level, thereby enhancing the efficiency of verification.
The components in the verification environment called a transaction processor . It is a static object that autonomously generate, handle or monitor the transaction. Conventional bus functional model that is a low-level transaction processor, the transaction will be converted into the excitation level of the design being tested object interface pins signal transition or vice versa. The higher level of transaction processor only transaction-level interfaces. Transaction processor according to the protocol design object used to process the transaction, in response to the measured design object generated from the pin switch response signal transitions back to the transaction-level form. This check can be done in response to the transaction level is correct, check out the response time does not match, it is further to be viewed on the signal / pin level, so as to locate the error out.
2 VMM verification methodology
VMM is based on SystemVerilog verification methodology. It takes advantage of the maximum program SystemVerilog object-oriented programming through a series of mechanisms which can achieve higher productivity.
2.1 hierarchical model validation
VMM uses a hierarchical structure is easy verification testbench reuse. Each layer that is built on top of other layers and has a certain independence, making verification platform use between different projects, even if a layer change will not affect the function of other layers reused, thus greatly improving the reusability of verification.
It can be seen VMM recommended hierarchical verification platform from the bottom-level signal is divided, layer order, layer function, and layer test scenarios layer. Wherein the verification element comprises a generator , a proxy, the drive , a monitor , check, a scoreboard and assertions.
Test DUT comprises a signal layer and the interface design. Command signal layer over the layer down is connected with the design of the test signal by the interface layer, the channel layer to communicate with the transaction-level functionality through upwardly, generally includes a driver (Driver), a monitor ( Monitor ) and assertions (Assertion). The drive conversion transaction from the upper stage to the excitation signal input DUT, changes in the monitoring interface to monitor signals transmitted to the upper layer and converted checker for the transaction. A functional layer located above layer order, high-level abstraction of the operation, transaction-level channel communicate with each other through. This layer includes an agent (Agent), Checker (Checker) and the scoreboard (Scoreboard). The agent role is to receive the upper level coming transaction, such as reading and writing DMA and the like, and converts these commands into a single transaction level provided to the driver. Drive receiving the command issued by the agent, it will generate data corresponding excitation. Scoreboard used to predict the dynamic response of the design, is applied to the excitation applied to the DUT while the scoreboard, the scoreboard conversion function converts all the excitation input into the final form of the response and stored in a data structure, for delivery to check , a scoreboard also record the number of affairs and statistics, records performed on all transactions, the number of success or failure of the transaction, whether a transaction is missing and so on. By checking the data from the monitor to the predicted scoreboard stored responses are compared to determine whether the test functions correctly. Scenario (Scenario) layer over the functional layer, is mainly used to generate the transaction random sequence having a certain relationship. The top layer is a test, he is used to configure different test cases, different definitions constraints. Throughout the verification project, functional coverage is automatically generated by simulation tools, testers to adjust the test platform based on functional coverage, modify until the test case coverage 1O0%, it can be considered the end of the verification process.
In order to make full use of the advantages of SystemVerilog an object-oriented programming language, the verification with class components (class) is achieved, in order to improve reusability, the entire verification platform unified framework structure becomes clearer and easier to maintain.
2.2 mechanisms for the VMM methodology to verify the productivity of science to improve the productivity of the project validation through four different mechanisms. These four mechanisms to do is: assertion, abstraction, automation and reuse.
Assertions are designed to check the behavior of the signal under test is correct viewer that is descriptive language implemented. By checking function provided in strategic locations inside the external interface module and its design, the need to write a separate test code, the test will be able to observe from outside the platform to what happens monitoring of these key points, can effectively improve the design and positioning of observation wrong ability.
The traditional bus functional model so hard for us to combine or add a new protocol layer, while the level of transaction processor forms the recursion level of abstraction, to overcome this limitation by bus functional model of hierarchical transaction processor.
In the verification, it is necessary to generate excitation driven design. For a limited time during the simulation, directed tests only verify the typical behavior of the chip, but can not verify all the possible behavior, which is the major drawback of directed tests. And randomizing excitation only a few lines of code can produce large amounts of stimulus data, to expand the verification test excitation signal space by providing a random design. When the random excitation source can not generate the required excitation signals, or can not be used without the required excitation focused random signal source randomizing excitation when generating verification may impose constraints on the randomisation process, it generates more falls within the area of interest to us or boundary, can meet the requirements of functional coverage more quickly.
VMM-level verification environment to be a clear definition, reflect the different levels of abstraction design process the data, and build each layer has a certain independence on the other layer, a layer even if the change does not affect the function reused by other layers, thus greatly improving the reusability of verification, which can effectively reduce the complexity of test cases to be written, verification environment without modification to be reused as many test cases to avoid rewriting the same functionality module .
Application Example 3
Following through an example describes how to set the transaction hierarchical verification platform, to a FIFO module under test DUT with the VMM. Verification platform top configuration shown in Figure 2:
Since the design is relatively simple, and therefore this layer is not a scene function module implemented. The individual components are used to verify image above classes. The following describes the functions and achieve the various top-down assembly verification.
(1) transaction definition fifo_tr
Vmm_data transaction fifo_tr it inherits from the VMM, and therefore inherits several methods vmm_data defined as copy (), compare () and the like. fifo_tr including two member variables kind and data, the former definition of the type of transaction is a read or write, which defines the data read and write.
(2) transaction channel fifo_chan
fifo_chan generated by the macro definition `vmm_channel VMM (), for transmitting a specific transaction between a transaction-level validation components. Compared with the structure SystemVerilog mailbox defined, it is strongly typed channel, i.e., each channel can only transmit a specific transaction, to avoid the occurrence of the error condition.
(3) Interface fifo_if
fifo_if is a communication interface between the driver and the FIFO, which encapsulates the Pin FIFO belonging to the signal layer, the driver through the interface to the actuating input to the DUT.
(4) generator fifo_gen
fifo_gen vmm_xactor base class inherits from the VMM, the core of which is an infinite loop, for generating a random transaction, such as a read transaction or a write transaction, and the transaction tunneled to the drive fifo_drv.
(5) Drive fifo_drv
fifo_drv vmm_xactor base class inherits from the VMM, and its function is to receive transactions from an upper layer fifo_xactn generator fifo_gen by analyzing a signal converted to a signal level, as measured excitation input to the FIFO design, its construction comprises two important parameter, one input channel is used to communicate with the generator, and the other is an output interface for communicating with the FIFO.
(6) Monitors fifo_mon
fifo_mon it inherits vmm_xactor from the VMM, and its function is to signal a change to monitor the FIFO, transfer the actual response will be designed to checker fifo_chk. and drive similar to its structure also contains two important parameters, one is an input interface , used to connect to the FIFO, the interface monitoring changes in the signal, the other is a transaction-level channel for communication with the inspector.
(7) checker fifo_chk
fifo_chk inherited from the VMM base class vmm_xactor, to check whether the transaction properly implemented. Specifically monitor the transmitted prediction result information transmitted from the scoreboard are compared to determine the correctness of the test function.
(8) scoreboard fifo_scb
Scoreboard inherited from the VMM base class vmm_xactor, used to generate input stimulus to predict the response, and the transaction has taken place to be documented with statistics, such as how many in total were read transaction or write transaction, which has been completed, which is linked to on, which of the transactions correctly implemented, during the execution of a transaction in which of wrong and so on.
(9) assertion assertions used to test the assertion offense to the FIFO, as written in the full circumstances FIFO, read FIFO empty case, these can be checked out by assertion. Framework described above to verify the platform assembly may be composed of validation Figure 3 as follows:
Top module tb_top the DUT, the test program (program), and the interface clock generator Composition. Example of a test program verification environment fifo_env, verify that all necessary environmental matters processor of cases, test cases only program (program) to achieve an initial block in the block, do so to avoid the design, assertions and verification environment Adventure competition occurs, and so that only one initial test case execution block is single-threaded, so that each step of the test case to be accomplished may be more readily understood.
4 Summary
Verify, on the increasingly high level of abstraction is evolving historical trends. In this paper, FIFO verification platform, for example the use of object-oriented thinking describes how to use the VMM verification methodology to establish hierarchical verification platform based on the transaction, a brief introduction to the function of each component level verification and implementation, given the overall verification platform frame. The verification platform with high reusability, enhanced readability, reducing maintenance costs verification platform, reflects the superiority of VMM verification methodology.
Author innovation: proposed use VMM idea of establishing a transaction-based hierarchical verification platform.
