1, scoreboard (Scoreboard)
Scoreboard used to predict the dynamic response of the design, is applied to the excitation applied to the DUT while the scoreboard, the scoreboard conversion function converts all the excitation input into the final form of the response and stored in a data structure, for delivery to check , a scoreboard also record the number of affairs and statistics, records performed on all transactions, the number of success or failure of the transaction, whether a transaction is missing and so on.
2, scenario (Scenario)
Scenario (Scenario), is mainly used to generate the transaction random sequence having a certain relationship.
3, the base class, the most commonly used generally have the following nine basic class:
vmm_env，vmm_xactor，vmm_channel，vmm_data，vmm_log，vmm_atomic_gen，
vmm_scenario_gen，vmm_notify，vmm_test。
VMM verification methodology, mainly constituted by a number of base classes authentication context verification methodology, wherein several basic classes must master as follows:
vmm_data: very important basic class, a lot of other classes are extended and extended its coming;
vmm_xactor: very basic class in mobile, applications are many, many other basic class is determined by its extended and extended from.
vmm_data and vmm_xactor learning focus VMM verification methodology is also difficult, it is important to understand thoroughly.
VMM verification methodology to improve project productivity through four different mechanisms. These four mechanisms to do is: assertion, abstraction, automation and reuse.
In this section you will find explanation of vmm base classes and architecture of the vmm based testbench.
vmm basic classes:
Index :
-- VMM log : Vmm log message example, macros, severity and method
-- VMM Data : VMM data class is used to model transaction, packet or item
-- VMM channel : Vmm channel is a inferface to connect the generators and transactors to pass the transaction object
-- VMM Xactor : All the running components like transactor, generator, monitor, scoreboard etc are deriverd from xactor class
-- VMM notify : VMM notify base class
-- VMM Atomic Gen : VMM atomic generator is used to generate the transaction randomly
-- VMM env : Verfication environments should be extened from vmm_env class
-- VMM Callbacks : Callbacks are used to change the behavior of a verification component without actually changing the compoent
vcs use common commands Detailed
+v2k
Enables language features in the IEEE 1364-2001 standard.
success报告成功匹配
Enables reporting of successful matches, and successes on
cover statements, in addition to failures. The default is to report
only failures.
filter过滤掉空成功。
Blocks reporting of trivial implication successes. These happen
when an implication construct registers a success only because
the precondition (antecedent) portion is false (and so the
consequent portion is not checked). With this option, reporting
only shows successes in which the whole expression matches.
-assert filter+success经常两者结合起来用。注意用时在filter+success前加上-assert
maxsuccess=N
Limits the total number of reported successes to N. You must
supply N, otherwise no limit is set. VCS continues to monitor
assertions even after the limit is reached.
-assert maxsuccess=3
-l filename logfile文件名
Specifies a file where VCS records compilation messages. If you
also enter the -R or -RI option, VCS records messages from both
compilation and simulation in the same file.
-assert enable_diag
Enables further control of results reporting with runtime options
-sverilog
Enables the use of SystemVerilog code.
-cm assert
Compiles for SystemVerilog assertions coverage. -cm is not a
new compile-time option but the assert argument is new. This
option and argument must also be entered at runtime.
vcs *.v *.sva -sverilog \
+define+enable_blk_assertions \
DEFINE tb_sva + + \
+ + slv_fc DEFINE \
+ + slv_doc DEFINE \
-PP -assert enable_diag -cm Assert \
-l compile.log
SIMV -assert -l run.log in the filter. 3 + = Success -assert maxsuccess
the VCS verilog model of the simulation consists of two steps:
1. compile verilog file becomes a command executable binary file is:
{}. 1 gt; the Source_Files VCS
2. run the executable file
{1} gt; ./simv
similar to NC, is also a single command the lines are:
{}. 1 gt; -R & lt VCS the Source_Files
-R & lt expressed command is executed immediately after compilation.
-cm line | cond | FSM | TGL | OBC | manner coverage path set
a FEW More Options are the compile Significant:
. 1 . IF RVM libs are Used in class at The OV code, the this IS required:
-ntb_opts RVM
2. the VMM classes, vmm_ Macros CAN BE Used in SV; and rvm_ Macros
Automatically Flag Inappropriate Content Package Penalty for OV are in vmm_ Core Sentences IF to
the this IS Also added
-ntb_opts Interop -ntb_opts RVM
-LCA
that VCS is a parameter that indicates the use of VCS "user limit the use of" function, that is, VCS provides some functions that they have not fully tested yet released; if you want to use these functions would add -lca parameters.
+ INCDIR + Directory
Specifies at The Directory or Directories that the VCS Searches for the include
Files Used in at The `the include Compiler Directive. More Within last One
Directory May BE specified, Separated by +.
+ plusarg_save
s Some Runtime Options the MUST BE preceded by at The + plusarg_save
the Option for the VCS Them at The Executable INTO the compile to. by You CAN
the Specify the this the Option at The ON either the Command Line or in the VCS at The File
specified with the Option at The -f or -F.
You can also enter the following runtime options on the vcs command
line or in the file that you specify with the -f or -F compile-time option,
so that VCS compiles them into the simv executable, BUT you must
precede them with the +plusarg_save compile-time option:
+cfgfile +override_model_delays
+vcs+dumpoff +vcs+dumpon
+vcs+dumpvarsoff +vcs+grwavesoff
+vcs+ignorestop +vcs+learn+pli
+vcs+mipd+noalias +vcs+nostdout
+vcs+stop +vera_load
+vera_mload +vpdbufsize
+vpddrivers +vpdfile
+vpdfilesize +vpdnocompress
+vpdnostrengths +vpdports
+vpdupdate
-ntb_opts dtm
You enable testbench constructs outside programs with the
-ntb_opts dtm compile-time option and keyword argument.
The testbench constructs that you can enter outside programs with
this option are as follows:classes associative arrays dynamic arrays
SystemVerilog named events
Work status: the establishment of a simulation environment
VCS Synopsys, Inc. is a simulation tool.
VCS verilog model for simulation involves two steps:
1. Compile verilog file becomes an executable binary file command is:
> vcssourcefiles2 run the executable file> vcssourcefiles2. run the executable file> ./simv
similar to NC, there are ways single command line:
$> the Source_Files the VCS -R
-R command, said immediately after the implementation of the compiler.
the following describes commonly used command options:
the -cm line | cond | fsm | tgl | obc | path set coverage the way
+ define + macro = value + precompiled macros
-f filename RTL file list
+ incdir + directory + add folders include
-I enter interface
the -l logfile filename
-P pli. tab lists the definition of PLI (tab) file
+ v2k use the recommended standard
-y Defined verilog library
-notice display detailed diagnostic information
-o name of the executable file output, default is sim.v
interface:
Note, interface is the DUT and testbench interface. Therefore, the interface can not simply be copied trouble signal port DUT top level design. Since the DUT interface and testbench interface port signals in different directions so that the direction of the top layer DUT port design.
assertion:
It should be noted, is embedded within the assertion to the design, the assertion signal list port module, for assertion itself, are acquaintances signal. Can not be defined in terms of signal direction signal list of port design, otherwise there will be compiled problem. Such as:
variable driven by a stuctural diver cannot have any other drivers.
