[Verilog combat] Configurable voting device design and functional verification (with source code)

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Virtual machine: VMware -14.0.0.24051
Environment: ubuntu 18.04.1 Script
: makefile ( click to go )
Utility: vcs and verdi

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1. Demand

  Realize the parameterized voting function, which can be configured as 2N+1 voting function, and the majority vote will pass. Define an N-bit input in in the module to represent N people participating in the voting, and then use the for loop to calculate how many bits in in are 1. If there are 1s greater than or equal to (N+1)/2 bits, it means the majority People agree, pass, otherwise do not pass.

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2. Block Diagram

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三、Design and Functional Verification

（1）RTL

//-- modified by xlinxdu, 2022/04/26

module vote
#(
  parameter NUM   = 3,
  parameter WIDTH = 2
)
(
  input                clk_i  ,
  input                rst_n_i,

  input      [NUM-1:0] in     ,
  output reg           pass_o
);

  reg     [WIDTH-1:0]  cnt ;
  integer              i   ;
  wire                 pass;

always @ (*) begin
  cnt = 2'b0;
  for(i=0;i<NUM;i=i+1) begin
    cnt = cnt + in[i];
  end
end

assign pass = (cnt >= ((NUM+1)/2))? 1'b1:1'b0;

always @ (posedge clk_i or negedge rst_n_i) begin
  if (!rst_n_i) begin
    pass_o <= 1'b0;
  end
  else begin
    pass_o <= pass;
  end
end
endmodule

（2）Test Bench

//-- modified by xlinxdu, 2022/04/26
module tb_vote;
  reg clk_i;
  reg rst_n_i;

  reg [2:0] in;
  wire      pass_o;

initial begin
  clk_i = 0 ;
  rst_n_i = 1;
  in = 3'b000;

  #10 rst_n_i = 0;
  #10 rst_n_i = 1;
end
always #50 in = {$random}%7;
always #25 clk_i = ~clk_i;

vote tb_vote(
              .clk_i(clk_i),
              .rst_n_i(rst_n_i),

              .in(in),
              .pass_o(pass_o)
 );

initial begin
  #10000 $finish;
  
  $fsdbDumpfile(".fsdb");
  $fsdbDumpvars            ;
  $fsdbDumpMDA             ;
end

endmodule

4. Result

  It can be seen from the above results that in the configuration N=3, if the majority of people voted more than or equal to two people, it means that the pass, pass output 1, the module data path is normal, and the function verification is passed.
Notice: When calculating the number, you need to initialize the value of cnt.

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Author: xlinxdu
Copyright: This article is the original author, and the copyright belongs to the author.
Reprinting: Reprinting is prohibited without the permission of the author. Reprinting must retain this statement, and a link to the original text must be given in the article.