Reproduced the original address: http://blog.chinaaet.com/justlxy/p/5100053262
Previous article introduced, each PCIe device can have only one function (Function), namely Fun0. You can have up to eight functions, namely multi-function devices (Multi-Fun). Regardless of the number of PCIe devices have functions, each of which has a corresponding function with only independent configuration space (Configuration Space).
And as a PCI bus, PCIe buses each function (Function) has a corresponding unique identifier. This identifier is BDF (Bus, Device, Function), PCIe configuration software (i.e., Root application layer, typically a PC) should have the ability to recognize the overall topology logic PCIe bus system, and wherein each of the bus (Bus), each device (device), and each function (function).
In the BDF, Bus Number occupy 8, Device Number occupancy 5, Function Number occupy three. Obviously, PCIe bus supports up to 256 sub-bus, each sub-bus supports up to 32 devices, each device supports a maximum of eight functions.
PCIe bus uses a depth-first (Depth First Search) algorithm topology, and Bus0 is always assigned to Root Complex. Root contains an integrated Endpoint and multiple ports (Port), each internal port has a virtual PCI-to-PCI bridge (P2P), and this should also be the bridge device number and function number.
It should be noted that each device must have a function 0 (Fun0), the other seven function (Fun1 ~ Fun7) are optional.
A simple example is shown below:
Note: topology logic on the PCIe bus will be described in detail in a later article.
Previous article introduced on the PCI bus configuration space of the PCI bus, PCIe bus for compatibility with these PCI devices, almost complete retention of configuration space PCI bus. And configuration space expanded to 4KB, the PCIe bus used to support some of the new features, such as PCI Express Capability, Power Management and MSI / MSI-X and so on.
The figure is inherited from the PCI bus over the configuration space:
The figure is a schematic view of the new PCIe configuration space:
