Address reprint: http://blog.chinaaet.com/justlxy/p/5100053476
First, recall that before many times looked Layer structure diagram of the PCIe:
PCIe physical layer is completed in the primary codec (8b / 10b for Gen1 & Gen2,128b / 130b for Gen3 and later), the scrambling code and descrambling code, serial-parallel conversion, differential transmission and reception, the link training and so on. Wherein the link training is achieved primarily by physical layer packet Ordered Sets.
PCIe Spec physical layer is divided into two parts - logical sub layer and an electrical sub-layers, as shown below:
As shown above, PCIe physical layer send and receive a pair of differential pairs, it is possible to realize full-duplex communication. Note that, PCIe Spec only provides the functionality, performance and other physical layer parameters need to be implemented, as to how to achieve them but did not expressly stated. In other words, manufacturers can according to their needs and circumstances, to design the PCIe physical layer. The following examples will be briefly Mindshare book section describes the PCIe physical layer logic, and may differ from other vendors physical layer device implementations, but the design goals and the ultimate function is substantially uniform.
FIG transmitting side portion structure of the physical layer logical sub layers as shown below:
Before 8b / 10b encoding, will Mux data from the data link layer insert some content, such as for marking the packet data and control characters or character boundary of Ordered Sets. To distinguish these characters, Mux their corresponding one D / K # bits (Data or Kontrol).
Note: The figure also includes some implementations Gen3, but here only Gen1 & Gen2, and will not introduce Gen3. If you are interested, you can go read the books or reference Mindshare PCIe Gen3 of Spec.
Byte Striping parallel data from Mux allocated according to certain rules (will detail later) to the respective Lane up. Followed by scrambling code (Scrambler), 8b / 10b encoding, serialization (the Serializer), then the differential transmission pair.
Wherein the scrambler (Scrambler) is based on a pseudo random code (Pesudo-Random) of the exclusive OR logic (the XOR), as is the pseudo-random code, so long as the sending and receiving ends use the same algorithm and the seed, the receiving end can easily recover the data. However, if the sending end and a receiving end for some reason it beats inconsistent, this time will produce an error, and therefore Gen1 Gen2 scrambler (Scrambler) is reset periodically.
Note: on principle and the role of 8b / 10b, and I have introduced in the previous blog post. So the next article will not repeat the description of these elements, but will briefly introduce PCIe implementation details and points of 8b / 10b's. Previous article address: http://blog.chinaaet.com/justlxy/p/5100052814
Receiving a configuration diagram of an end portion of the physical layer logical sub layers as shown below:
Since the PCIe uses a Embeded Clock (by 8b / 10b) mechanism, the receiving terminal when receiving the data stream, the first clock signal recovered from, this is achieved by CDR logic. As shown above, substantially all logical receiving end corresponding to the end opposite to the transmission operation. Here it is not described in detail.