Reproduced the original address: http://blog.chinaaet.com/justlxy/p/5100053321
Previous article describes the role and usage type Configuration Space Header Type0 of BAR, but the bridge device (Switch and P2P Root in) PCIe in is how to determine a request (Request) whether their own or their branch equipment under it? This is actually achieved by Type1 type of configuration space Header Base and Limit registers this article to brief you.
Base and Limit registers Type1 Header in a position as shown below:
Base and start and end addresses are determined Limit registers all of its devices (The device that live beneath this bridge) at the branch address. The different request types, corresponding to different combinations of Limit & Base:
· Prefetchable Memory Space（P-MMIO）
· Non- Prefetchable Memory Space（NP-MMIO）
· Space IO (IO)
Once the BAR any equipment changes below the bridge branch, the bridge Base & Limit register also need to make the corresponding changes.
Below a simple example, to analyze:
As shown above, the PCIe Endpoint connected to the Switch PortB are arranged NP-MMIO, P-MMIO and IO space. Let's briefly analyze PortB in the Header Base & Limit register.
P-MMIO Base & Limit
NP-MMIO Base & Limit
It should be noted, NP-MMIO size of Endpoint need obviously only 4KB, PortB the Header gave its 1MB of space (minimum 1MB), that is to say all the remaining space will be wasted, and all the other Endpoint You will not be able to use this space.
IO Base & Limit
Note: The minimum value can be allocated IO space is 4KB, and the maximum value depends on the operating system BIOS.
Unused Base and Limit Registers
In many cases, we do not need all of the address space type, such as one where the Endpoint not used IO Space. In this case, Base Header will bridge its corresponding address to the address larger than the Limit, the address range is set to invalid.
A complete example is shown below:
