Preface
The summary of written test questions is to summarize the problems that may be encountered in the autumn recruitment. Solving the questions is not the purpose. The purpose is to discover your own loopholes in the process of doing the questions and consolidate the foundation.
All question results and explanations are given by the author. The answers are highly subjective. If there are any errors, please point them out in the comment area. The information is compiled from digital IC-related public accounts such as "Digital IC Workers", real questions from websites such as Niuke.com, and online written tests. Transcripts of real questions and interviews.
Keep updated (2023.9.25) The article contains 270 single-choice questions, 106 multiple-choice questions, 16 fill-in-the-blank questions, 17 true-false questions, 72 short-answer questions, 3 logical reasoning questions, and 8 C language python script programming questions Tao .
All the codes provided by the author in this article are written as APIs and can be directly copied to the software to compile, run, and give results.
There are many questions, and even with previous analysis and the powerful ChatGPT, mistakes are inevitable. If you find any mistakes, please feel free to discuss them in the comment area.
In addition, there is a little personal stuff~: At this moment, I feel that I must give...
The total number of words in the solution to the Thousand Questions of the Digital IC Written Test has reached 150,000+, and the webpage is severely stuck in coding, so it is divided into multiple parts to facilitate maintenance. The link is as follows: Solution to the Thousand Questions in the Digital IC Written Test--Single Choice Questions (1)
Digital
IC Solutions to Thousands of Questions in the Written Test - Single-Choice Questions (Part 2) Solutions to
Thousands of Questions in the Digital IC Written Test - Multiple-Choice Questions (Part 3) Solutions to Thousands of Questions
in the Digital IC Written Test - Fill-in-the-Blank Questions (Part 4) )
Solutions to Thousand Questions in Digital IC Written Test - True and False Questions (5)
Solutions to Thousand Questions in Digital IC Written Test - Short Answer Questions (6) Solutions to
Thousand Questions in Digital IC Written Test - Logical Reasoning (7)
Solutions to Thousand Questions in Digital IC Written Test - Programming && Scripting Chapter (8)
Multiple choice questions
1. When a signal crosses the clock domain, a metastable state will occur. What factors are related to its failure?__________
A. The flip rate of the register output signal at the signal transmitting end
B. The register clock frequency at the signal transmitting end
C. The register clock frequency at the signal receiving end
D. The number of stages of the synchronization register
Answer: A,B,C,D
Flip rate : refers to the number of times the output of a logic gate changes from low level to high level or from high level to low level within unit time.
A. The flip rate of the high memory output signal at the signal transmitting end: The occurrence of metastable state is caused by the timing relationship during the signal transmission process. Signals with high flip rate are prone to timing problems during the transmission process, resulting in metastable state. of production.
B, C: Clocks with different frequencies transmit data, which may cause metastability.
D. The number of stages of synchronization registers: The more stages of synchronization registers, the greater the delay in signal transmission, thereby increasing the risk of metastability.
2. Which Verilog writing methods cannot be synthesized__________
A. Division whose input is a variable
B. For loop whose loop boundary is not specified at compile time
C. Function function containing a sequential circuit
D. Multiplication whose input is a variable
Answer: B,C. Option A division can be synthesized, but it may cause a large delay and consume a lot of resources. It is not recommended to write "/" directly.
3. The correct statement about asynchronous fifo is ____________
A. The reset signal of the asynchronous fifo can be used directly after clock synchronization.
B. The read and write pointers need to be processed through Gray code.
C. During use, the read and write clock can be synchronous.
D. When the address Gray code passes through the domain, the signal Delay must be less than 1 period of source clock
Answer: B,C.
Option A: The reset signal of the asynchronous FIFO should not be used directly through the clock synchronizer, because the reset signal of the asynchronous FIFO is not synchronized with the read and write clock, and there will be asynchronous situations. When using the reset signal of an asynchronous FIFO, it is usually necessary to use a special synchronization circuit to synchronize it to ensure that it is synchronized to the timing of the read and write clock.
Option D, under special circumstances, it may take longer to complete signal synchronization, and the signal delay can be greater than 1 source clock cycle.
4. The following statement about clock is correct_____________
A. Combination control logic such as OAI can be used on the clock path.
B. The clock can be used as data.
C. Use rising edge triggered logic as much as possible in the design.
D. The smaller the clock jitter, the better.
Answer: A,B,C,D. Option A, clock gating is controlled by OAI (OR and NOT) gates. Option B, in the encryption and decryption circuit, the clock signal can be used as part of the key or as a parameter in the algorithm. Option C, the stability of the rising edge of the clock is usually better than that of the falling edge. Option D, Clock jitter refers to the clock jitter of the clock signal. The smaller the jitter, the more stable the clock.
5.Hold violation can be solved by __________
A. Reduce the working voltage
B. Increase the working voltage
C. Insert clk buffer on the capture clock path
D. Reduce the clock frequency
E. Increase the clock frequency
F. Insert delay cell on the data path
Answer: A,F. Changing the clock frequency has no effect on hold violation because there is no clock cycle in the calculation formula of hold violation. Lowering the operating voltage can increase the time of ck_to_Q, which is helpful to avoid hold violation. Option C, inserting the clock buffer will only change the clock latency. In the calculation formula of hold violation, clock latency will be eliminated, so changing it will not affect the hold time slack.
6.The following statement is correct __________
A. When the operating voltage is reduced from 1.0V to 0.9V, the system power consumption will be reduced by 20%.
B. When the process is upgraded from 0.18um to 0.13um, while the operating voltage and frequency remain unchanged, the chip area is reduced and the power consumption is not.
The leakage power of C.85C is 10 times that of 25C . Reducing the system clock frequency by half and doubling the
system running time will reduce the system power.
Answer: D. Option A, the dynamic power consumption calculation formula is: CV^2*f. Without considering static power consumption, the operating voltage is reduced to 0.9V, and the dynamic power consumption is reduced to 81% of the original value, which is inconsistent with the option description. However, in the case of absolute multi-selection, BC is definitely wrong and AD can be selected. Option B, the power consumption will become smaller because the trace capacitance will become smaller. Option C: According to statistics, the leakage of 85c is about 8 times that of 25c, that is, for every 20 degrees increase in temperature, the leakage doubles.
7. Which of the following are third-generation mobile communication standards?
A EDGE
B TD-SCDMA
C LTE
D WIFI
Answer: B.
The third generation mobile communication standard usually refers to the 3G standard, which mainly includes the following:
-
CDMA2000 (Code Division Multiple Access 2000): It is a 3G standard developed by 3GPP2 (3rd Generation Partnership Project 2). It is mainly used in North America and the Asia-Pacific region to provide high-speed data transmission, voice and multimedia services.
-
WCDMA (Wideband Code Division Multiple Access): It is a 3G standard developed by 3GPP (3rd Generation Partnership Project). It is mainly used in Europe and Asia and supports high-speed data transmission, voice and multimedia services.
-
TD-SCDMA (Time Division-Synchronous Code Division Multiple Access): It is a 3G standard independently developed by China. It is mainly used in China and supports high-speed data transmission, voice and multimedia services.
-
WiMAX (Worldwide Interoperability for Microwave Access): It is a 3G standard formulated by IEEE (Institute of Electrical and Electronics Engineers). It uses OFDM technology and is mainly used in the field of broadband wireless access.
A. EDGE is a high-speed mobile data transmission technology used in GSM networks. Its rate can reach 384kbps and it belongs to the 2.5G mobile communication standard.
B. TD-SCDMA is one of the 3G mobile communication standards independently developed by China. Its full name is Time Division-Synchronous Code Division Multiple Access.
C. LTE (Long-Term Evolution) is a 4G mobile communication standard and one of the current mainstream 4G technologies. It has the characteristics of high-speed data transmission, low latency, and high reliability.
D. WIFI is a local area network technology, which belongs to the wireless LAN standard. Its speed is usually fast, but its coverage is small, and it is suitable for small-scale networks such as homes or offices.
8. Which of the following options cannot eliminate hold time violation ()
A Insert buff
B Increase clock frequency
C Decrease clock frequency
D Increase voltage
Answer: B,C,D. Option A, inserting a buffer at the data end can make the data arrive at the next register later (increase logic delay), thus alleviating the hold time violation. According to STA theory, there is no clock cycle in the hold time slack calculation formula, so changing the clock frequency will not improve the hold time violation. Option D, increasing the voltage will cause the transistors in the circuit to charge and discharge faster, causing data to arrive earlier, making hold time violations more likely to occur.
9. Which of the following are verification methodologies based on Systemverilog? ()
A VMM
B OVM
C UVM
D AVM
Answer: A,B,C,D.
10. Which of the following methods can be used to check timing ()
A Immediate assertion
B Development assertion
C Establishment time constraint
D Guard time constraint
Answer: C,D. All belong to the timing analysis part.
11. What adverse effects will there be if the power density in the design is too high ()
A Hot-spot
B Voltage drop
C Timing constraints are not met
D Packaging cost becomes higher
Answer: A,C,D. Option A, when the power density designed in the chip is too high, a local temperature increase will occur, that is, a "hot -spot " will appear . Option B, the increase in temperature causes the critical voltage of the transistor to decrease , which may cause the electrical performance of the circuit to change, leading to unstable circuit behavior, failure to meet timing constraints and other issues . Option D, the temperature increase will also have adverse effects on the packaging. For example, it may cause the packaging material to fail, thereby increasing the packaging cost .
12. What are the verification dimensions of digital circuits ()
A Completeness
B Reusability
C Efficiency
D Satisfying performance
Answer: A,B,C,D. Reference Blog: A Comprehensive View of Chip Verification Part 3: Five Dimensions of Verification Capabilities_OnePlusZero’s Blog-CSDN Blog
13. Which of the following descriptions of code coverage is wrong during verification ()
A Code coverage includes statement coverage
B Code coverage includes condition coverage
C Code coverage includes functions
D Code coverage reaching 100% means that all bugs have been cleared
Answer: C,D. Code coverage does not include functional coverage, but only the coverage of code execution paths.
14. In the following description of the new operation in systemerilog, the wrong one is ()
A It can be used to dynamically create objects and object data
B Use it to call the constructor when creating an object
C The new operation is defined as a function that needs to have a return type
D When using it to create an object array, you must specify the initial value of the object
Answer: C,D. The constructor not only allocates memory but also initializes variables. By default, it sets variables to default values (0 for binary variables, X for four-valued variables), and so on. You can set the default value to the value you want by customizing the new function. So the new function is also called a "constructor". But the new function cannot have a return value, because the constructor always returns a handle pointing to the class object, and its type is the class itself.
15. Which of the following descriptions of synchronous logic circuits and asynchronous logic is correct ()
A Synchronous logic circuit has no fixed causal relationship between clocks. Asynchronous logic circuit has fixed causal relationship between clocks.
B Synchronous logic is a circuit composed of sequential circuits (registers and various flip-flops) and combinational logic circuits. All its operations are completed under strict clock control.
C Asynchronous logic circuits do not require clock synchronization between different clock domains.
D Asynchronous logic may have multiple clock signals, or there may be no clock signals. A change in one logic in the circuit will cause a change in the logic of the entire circuit.
Answer: B,D. Option A is the opposite. Synchronous logic circuits are driven by clock signals, and there is a fixed phase relationship between each clock signal, while asynchronous logic circuits are not driven by clock signals, and there is no fixed phase relationship between different parts. Option C, cross clock and need to be synchronized.
16. In order to achieve high-speed design in VLSI circuit design, which of the following measures should be taken ()
A Pipeline design
B Parallel design
C Resource sharing
D Serial design
Answer: A,B. Option A cuts the pipeline and reduces the combinational logic delay between registers, which can increase the maximum operating frequency of the system and achieve high-speed design. Option B, parallel design, improves system performance several times at the expense of several times resources. Option C, resource sharing helps reduce area and power consumption. Option D, serialized design will cause the system speed to decrease, so it is not a measure for high-speed design.
17. How can the phenomenon of competitive risk-taking be eliminated? ()
A Add filter capacitor
B Introduce synchronization mechanism
C Do not add strobe signal
D Add redundant logic
Answer: A,B,D. Option A, add a filter capacitor to filter out burrs and at the same time smooth the narrow pulses. Option B, add a synchronization mechanism to eliminate signal competition caused by inconsistent combinational logic transmission delays. Option D, add redundant logic to improve the problem of inconsistent delay in the combinational logic transmission path, thereby avoiding signal competition.
18. Which of the following statements about Setup/Hold Time is correct? ()
A If the Hold time of DFF is not satisfied, it can usually be solved by increasing the data path delay.
B If the Setup time of DFF is not satisfied, it can usually be solved by increasing the data path delay.
C If the Hold time of DFF is not satisfied, it can usually be solved by Increase the clock path delay to solve
D If the setup time of DFF is not satisfied, it can usually be solved by increasing the clock path delay.
Answer: A,D. Data path delay refers to the delay in data transmission from the previous DFF to the next DFF. The clock path delay refers to the delay t2 from the clock to the next DFF minus the delay t1 from the clock to the previous DFF. Increasing the clock path delay allows the latter register to be sampled more slowly, which helps avoid setup violations. Reducing the clock path delay allows the latter register to sample faster, which helps avoid hold violations.
The hold time of the DFF is not satisfied, which means that the speed of the DFF after the data arrives is too fast, and the data is updated before it is kept long enough. Therefore, the clock path delay can be solved or shortened by increasing the data path delay . Let the sampling time of the latter register be earlier, and choice A is correct. The setup time of DFF is not satisfied, which means that the time for data to arrive in the next register is too slow. It should arrive before the data sampling window of the next register DFF. You can pass
19. Which of the following data types belong to the four-state type ()
A int
B logic
C bit
D time
Answer: B,D.
To summarize the system verilog variable data types:
Four-valued logical types: integer, reg, logic, wire, tri, time.
Binary logical types: byte, shortint, int, longint, bit.
Signed types: byte, shortint, int, longint, integer.
Unsigned types: bit, logic, reg, wire, tri, time.
Question 6 of the short answer question has a screenshot of the sv data type in the Green Book for reference.
20. The methods to implement low-power circuits are ()
A Reduce the operating voltage
B Increase the load capacitance
C Reduce the circuit area
D Improve circuit performance as much as possible
Answer: A,C. Option B, increasing the load capacitance will cause the circuit to require more charge movement when charging and discharging, thus requiring more current, resulting in increased power consumption. Option D, improving circuit performance (increasing clock frequency) will increase dynamic power consumption.
21. Please find the serial bus () among the following buses
A AXI
B SDIO
C UART
D IIC
Answer: C,D.
-
AXI (Advanced eXtensible Interface) bus: It is a high-performance, scalable on-chip bus proposed by ARM that supports high bandwidth and multi-processor access. Mainly used in SoC (System on Chip).
-
SDIO (Secure Digital Input/Output) bus: It is an input and output interface specially used for storage devices (such as SD cards, MMC cards, etc.), which can support high-speed data transmission and secure data storage.
-
UART (Universal Asynchronous Receiver/Transmitter) bus: It is an asynchronous serial communication bus used to transmit data from one device to another device. Commonly used for data transmission between computers and external devices (such as modems, printers, etc.).
-
IIC (Inter-Integrated Circuit) bus: It is a serial bidirectional communication bus used to connect integrated circuit chips and other peripherals. It is mainly used for short-distance, low-speed communication, such as connecting temperature sensors, EEPROM and other devices.
It should be noted that although UART and IIC are both serial buses, their application scenarios and transmission methods are different. UART is an asynchronous transmission, that is, each data byte has a start bit and a stop bit, while IIC is a synchronous transmission and does not require a start bit and a stop bit.
22. Which of the following methods can reduce the impact of metastability problems ()
A Increase the system clock frequency
B Use faster response FF
C Increase the data toggle rate on the architecture
D Improve the clock quality
Answer: B,D. Using FF with faster response can reduce T ck_to_Q and help avoid setup violation. Improving clock quality will help reduce the impact of clock jitter on timing.
23. Regular expressions describe a string matching pattern, which can be used to check whether a string contains a certain substring, replace the matching substring, or extract a substring that meets a certain condition from a string, etc. Characters A set refers to a collection of various pattern characters that can be matched at a single position. The abbreviations of some character sets are as shown in the following table.
| abbreviation |
match |
| \d |
decimal number |
| \D |
non-decimal number |
| \s |
White space characters |
| \S |
non-whitespace characters |
| \w |
Word characters ([A-Za-z0-9_]) |
| \W |
non-word characters |
| \n |
newline character |
May I ask: Which of the following options can be matched by "\W*\s*input\s*wire\s* (\[\d+\:\d+\])*\s* (\w+)\s*"?
A. input wire [3:0] num1
B. // input wire num2
C. // input wire [WIDTH-1:0] num3
D. Input wire [10:0] num4
E. input wire [BIT:0] num5
Answer: A,B. \W* matches as many non-word characters as possible; \s* matches as many whitespace characters as possible; input string; \s* matches as many whitespace characters as possible; wire string; \s* matches as many whitespace characters as possible; circle Brackets represent grouping (\[\d+\:\d+\])*, matching as many strings of the form "[number:number]" in the string as possible; \s* matches as many blank characters as possible; (\ w+) matches as many word characters as possible; \s* matches as many whitespace characters as possible. Here * means 0-more; + means 1-more.
Option C, WIDTH error; D option, Input error; E option, BIT error.
24. The following are DFT fault models: ()
A.stuck-at
B.transition-delay
C.brige
D.IDDQ
Answer: A,B,C,D
Stuck-at fault is the most commonly used fault model. There is a problem with some interconnection lines, causing the level on the line to be permanently fixed at 0 or 1.
Bridging Faults Bridging Faults occur when two or more interconnecting wires in a circuit are accidentally connected together.
Transition Delay Faults Transition faults fail to flip from 1 to 0 or from 0 to 1 within the expected time due to the delay of the faulty logic gate node.
IDDQ Faults: The quiescent current of the chip is relatively high when it is working, causing the voltage to drop and affecting the normal operation of the chip.
Reference blog: Testability design study notes_lu-ming.xyz's blog-CSDN blog
25. The following are the comprehensive quality evaluation indicators of the clock tree in the chip:
A. Clock network delay
B. Clock information deviation
C. Clock cycle
D. Clock tree power consumption
Answer: A,B,D.
A. Clock network delay: The transmission delay of the clock signal from the source to each clock flip-flop affects the timing constraints of the chip. The smaller the delay, the better.
B. Clock information deviation: After the clock signal passes through a long path, due to the influence of factors such as the temperature and voltage of the transistor, clock information deviation may occur, resulting in timing violations. Therefore, it is necessary to compensate for the deviation or add a clock calibration circuit.
D. Clock tree power consumption: The power consumption of the clock tree should be as small as possible, but if it is too small, the delay of the clock tree will be too large, affecting the performance of the chip. Therefore, clock tree power consumption and clock tree delay need to be balanced in clock tree synthesis.
26. The following methods are used to reduce the static voltage drop of the chip: ()
A. Increase power network density
B. Reduce package inductance
C. Increase chip capacitance
D. Reduce work efficiency
Answer: A,B,C,D.
Option A, increasing the power network density can improve the chip's power supply stability, reduce the impact of power fluctuations on the chip's static voltage drop, and reduce the chip's static voltage drop.
Option B, reducing the package inductance can reduce the inductance value, thereby reducing the impact of the inductance on the chip's static voltage drop and reducing the chip's static voltage drop.
Option C, increasing the capacitance within the chip can improve the capacitive properties of the chip, thereby reducing the resistance value of the chip and reducing the static voltage drop.
Option D, reducing operating efficiency can reduce static pressure drop.
27. Regarding asynchronous processing, which of the following statements is correct?
A. Static configuration signals do not need to be asynchronously processed.
B. Asynchronous processing needs to consider the frequency relationship between the sending and receiving clocks.
C. The reason why asynchronous FIFO uses Gray code is to improve the circuit speed.
D. A single-bit signal can be processed after two beats. Avoid the occurrence of metastability
Answer: A,B.
Option C, the asynchronous FIFO uses Gray code to solve the problem of uncertain status during data conversion, rather than to increase circuit speed.
Option D, two beats of a double-bit signal cannot completely avoid the occurrence of metastable problems, but only reduces the possibility of metastable problems.
28. Which of the following gate circuits are universal logic gates (can be combined to build any logic circuit) ()
A.AND
B.NAND
C.OR
D.NOR
E.XOR
Answer: B,D. NAND gate and NOR gate.
Reference blog: Logic circuit nand_Universal logic gate (NAND, NOR)_cumt30111's blog-CSDN blog
29. Which of the following are the characteristics of AHB?
A.split transaction
B.burst transfer
C.non-tristate implementation
D.out-of-order data transmission
Answer: A,B,C. Out-of-order sending is a feature of AXI.
AHB is mainly used for connections between high-performance modules (such as CPU, DMA and DSP, etc.). As the on-chip system bus of SoC, it includes the following features:
Single clock edge operation;
Non-three-state implementation;
Support burst transmission;
Support segmented transmission;
Support multiple main controllers;
Configurable 32-bit~128-bit bus width;
Supports the transmission of bytes, halfwords and words.
Pipeline approach
Complete the transfer of bus control from the bus master (master) within one cycle
30. Please select the following on-chip buses that can implement burst transmission
A.APB
B.AHB
C.SPI
D.AXI
Answer: B,D. APB and SPI do not support burst transmission. This requires you to learn AMBA bus 4.0 and common serial bus operating rules.
31. Which of the following descriptions of synchronous logic circuits and asynchronous logic circuits is correct?
A Synchronous logic circuit has no fixed causal relationship between clocks, while asynchronous logic circuit has fixed causal relationship between clocks. B Synchronous logic is a
circuit composed of sequential circuits (registers and various flip-flops) and combinational logic circuits. All its
operations are completed under strict clock control.
C There is no need for clock synchronization between different clock domains in asynchronous logic circuits.
D Asynchronous logic may have multiple clock signals, or there may be no clock signals. A change in one logic in the circuit will
cause a change in the logic of the entire circuit.
Answer: B,D. Option A is the opposite. Option C, error, clock synchronization is required between clock domains in asynchronous logic circuits, otherwise problems such as data errors and steady-state oscillation may occur.
32. In VLSI design, which of the following measures should be taken for high-speed design?
A. Pipeline design
B. Parallel design
C. Resource sharing
D. Serial design
Answer: A,B. Pipelining and parallelization are both cases of area trading for speed.
33. What are the interface mechanisms between Verilog and other programming languages?
A.PLI
B.DPI
C.NPI
D.VPI
Answer: A,B,C,D
PLI (Programming Language Interface) is the original extended interface of Verilog, which allows users to embed custom functions into the Verilog simulator through a dynamic link library written in C language. These functions can be called by testbench in Verilog to provide some additional simulation control and data analysis capabilities.
NPI (Native Programming Interface) is an extended interface in SystemVerilog that provides a new and simpler way to achieve interoperability between Verilog and C/C++. Unlike PLI, NPI is implemented in C++ language, allowing users to write code in native C++ without using C language and dynamic link libraries.
Verilog can be integrated with the interfaces of EDA tools, such as simulators, synthesizers, layout and routing tools, etc. for interface communication. These interface mechanisms usually use VPI (Verilog Programming Interface) or DPI (Direct Programming Interface).
34. Which of the following information does UPF describe ( )?
A.power distribution architecture
B.power data
C.power strategy
D.usage of special cell
Answer: A,B,C,D.
UPF (Unified Power Format) is a format used to describe chip-level power management information, which includes design elements used to control power management, such as power domains, power modes, power nets, power objects, etc.
Option A describes the power network architecture; Option B describes the power requirements, power consumption limits and other information of each power domain. Option C, power consumption strategy. Option D, using special cells for power management is a technology often used in UPF descriptions. Special units are circuit units with special power control functions that can be used to provide more refined power management capabilities.
35. What specific aspects of PPA do chip design focus on?
A.Performance
B.POWER
C.Architecture
D.Area
答案：A,B,D。PPA，power、performance、area。
36. Code coverage mainly includes
A.Row coverage
B.Condition coverage
C.toggle coverage
D.Function coverage
Answer: A,B,C.
Code coverage mainly includes:
-
Line Coverage: refers to the proportion of executed lines of code to the total number of lines of code.
-
Branch Coverage: refers to the proportion of all possible execution paths covered for branch structures such as if statements and switch statements.
-
Condition Coverage: refers to the proportion of all possible Boolean expression values that are covered.
-
Path Coverage: refers to the proportion of all possible paths in the code that have been executed.
-
Toogle Coverage: Toogle Coverage measures which single-bit variables have a value of 0 or 1, indicating the 0 to 1 and 1 to 0 flips of signals in the code.
6. Finite state machine coverage (FSM coverage): Finite state machine coverage measures which states and state transitions in the state machine have been visited. Indicates the coverage of each state in the state machine.
37. Which of the following statements about code coverage is incorrect during verification?
A. Code coverage includes statement coverage
B. Code coverage includes condition coverage
C. Code coverage includes functions
D. Code coverage reaching 100% means that all bugs have been eliminated
Answer: A,B. Option C, code coverage does not include functional coverage. Option D, code coverage can only mean that all parts of the code have been run, but it does not mean that the functions are correct.
38. During EDA verification, which of the following methods can be used to check timing?
A. Immediate assertion
B. Concurrent assertion
C. Setup time constraint
D. Guard time constraint
Answer: C,D. Assertion is a requirement for functional verification. It does not directly check the circuit timing, but checks whether the circuit meets the design specifications by verifying the logical behavior.
39. Which of the following are power special cells ( )?
A.buffer
B.level shifter
C.power switch
D.isolation
Answer: B,C,D.
A. buffer: Buffer, used to provide amplification and buffering functions on the signal path.
B. level shifter: Level shifter, used to convert one level to another level, usually used between circuits with different power supply voltages.
C. power switch: Power switch is used to turn the power on or off in the circuit to control the power consumption of the circuit.
D. isolation: Isolation unit, used to isolate power or signals in a circuit to prevent signal conflicts or circuit damage.
40. Which statement is correct about pipeline design of sequential logic circuits ( )?
A.Pipeline can improve the throughput rate
B.Pipeline can reduce the latency of a single task
C.Pipeline can increase the clock frequency
D.Pipeline needs to cut the pipeline, and the pipeline must be balanced during design to ensure that the timing is close
Answer: A,C,D.
Pipeline only improves the throughput of the system, but cannot improve the latency of a single task.
41. Which of the following factors are considered to evaluate the quality of a clock tree? ( )
A.Insertion delay
B.Skew
C.Local cell density
D.Dynamic power consumption
Answer: A,B,C,D.
The quality of the clock tree is usually evaluated from the following aspects:
-
Clock skew and jitter: The design of the clock tree should minimize clock skew and jitter to ensure the stability of the clock signal throughout the chip.
-
Clock power consumption: The clock signal is one of the most power-consuming signals in the chip, and the clock tree should be designed to reduce power consumption as much as possible.
-
Clock frequency: The design of the clock tree should make the clock frequency stable and reduce clock cycle changes and fluctuations.
-
Clock delay: The design of the clock tree should reduce the clock delay, ensure the transmission speed of the clock signal, and reduce the impact of the clock tree on the performance of the chip.
-
Clock distribution: The clock tree should be designed to be distributed as evenly as possible on the chip to avoid problems caused by clock signals being too dense in certain areas, such as clock insertion, clock jitter, and EMI.
-
Testability of the clock tree: The design of the clock tree should consider testability to facilitate subsequent testing and troubleshooting.
-
Cost of the clock tree: The design of the clock tree should consider cost factors, including costs in design time, layout area, power consumption, etc.
42. We need to define clock specification in SDC file, using commands like below:
create_clock -name GFXCLK -period 600 -waveform {0 300}
what can we know from this command? ()
A.Clock frequency
B.Clock duty cycle
C.Clock source latency
D.Clock name
Answer: A,B,D. -name gives the name, -period gives the duty cycle, waveform {0 300} indicates that the starting time of the clock signal is 0 nanoseconds, and the clock period is 300 nanoseconds.
43. Why should we use double width and double spacing rule for clock net routing? ()
A.Reduce resistance
B.Avoid noise
C.Increase capacitance
D.Take more routing resource
Answer: A,B. Resistance can be reduced with larger line widths. Using a larger line spacing can reduce the coupling current between wires, reduce noise, and reduce capacitance.
44. Developing FPGA or ASIC solution to meet same function requirement. Which description are correct? ( )
A. FPGA is fast time to market
B. FPGA is more flexible to be developed and programmed in keeping changing area
C. ASIC’s per chip cost is cheaper
D. FPGA has better power performance
Answer: A,B,C. FPGA is indeed more flexible than ASIC, but the average cost of ASIC will be lower than FPGA, and ASIC is an application-specific integrated circuit, which does not add a lot of logic for programming flexibility like FPGA, so ASIC power consumption will be much less than FPGA, so choose ABC .
45. Which among the following types are USB Transfer types? ( )
A.Control Transfer
B.Isochronous Transfer
C.Asynchronous Transfer
D.Interrupt Transfer
E.Bulk Transfer
Answer: A, B, D, E.
USB (Universal Serial Bus) is a commonly used serial bus standard used to connect computers and various peripheral devices to achieve functions such as data transmission and power supply. In the USB standard, data transmission can be divided into the following types:
-
Control Transfer: Used to transfer command and control information between the USB device and the host, such as setting the device address, reading the device descriptor, etc. Control Transfer is a data transfer type that must be supported.
-
Bulk Transfer: Used to transfer large amounts of data without ensuring real-time performance and reliability. It is suitable for applications such as printers and storage devices.
-
Interrupt Transfer: used to transmit real-time data, requiring low latency and reliability, suitable for mouse, keyboard and other applications.
-
Isochronous Transfer: Used to transmit time-sensitive real-time data, such as audio and video data, etc. It is necessary to ensure the stability and real-time performance of data bandwidth and transmission rate.
46. About MOSFET, which is/are right? ( )
A.gm=Ig/Vgs
B.MOSFET consist of mental, oxide and semiconductor
C.Improving W/L can increase the Ig
D.The channel direction of MOSFET is related to crystal orientation
Answer: B,C. Option A,gm=△Ig/△Vgs. Option D, the channel direction has nothing to do with the crystal orientation, and the voltage is related to the substrate.
47. Which are proper prototype? ( )
A.Int funct(char x, char y);
B.Double funct(char x);
C.Void funct();
D.Char x();
Answer: A,B,C. Option D, first of all, [] should be used when declaring an array, and secondly, the length of the declared array is not given.
48. The following measures of DFT quality are: ( )
A. Test coverage
B. Test circuit area overhead
C. Test time
D. Fault model
Answer: A,B,C.
The quality of DFT (Design for Testability, design for testability) mainly considers the following indicators:
-
Fault Coverage: refers to the proportion of faults that can be detected by the test set to all possible faults. The higher the fault coverage, the better the testability of the design.
-
Test Pattern Count: refers to the number of test patterns in the test set required for the design. The smaller the number of test patterns, the better the testability of the design.
-
Test Time: refers to the time required to conduct a complete test. The shorter the test time, the higher the test efficiency and the better the testability of the design.
-
Flexibility: refers to whether the designed test method is suitable for various testing needs. The greater the flexibility, the higher the testability of the design.
-
Reliability: refers to the accuracy and stability of test results. The higher the reliability, the better the testability of the design.
-
Design Overhead: refers to the design overhead required to increase testability. The smaller the design overhead, the better the testability of the design.
49. Which of the following descriptions of OCC (on chip clock controller) behavior is correct: ( )
A. Used to control the switching of high-frequency and low-frequency test clocks
B. Used to control the generation of a specified number of shift clocks
C. Used to control the generation of a specified number of capture clocks
D. The switching process may produce glitches
Answer: A,B,C. Option D, OCC is a circuit composed of registers and will not generate glitches.
OCC (On-Chip-Clock) meaning, function and structure_cy413026's blog-CSDN blog
50. The following are inspections before chip tape-out: ( )
A. Design rule check
B. Antenna effect check
C. Circuit and layout consistency check
D. Formal verification
Answer: A,B,C.
Inspections before chip tape-out mainly include the following aspects:
1. Logic circuit inspection: Comprehensive logic verification of the schematic diagram of the designed circuit, including verification of logic correctness, timing correctness, timing closure, etc.
2. Physical circuit inspection: Conduct comprehensive electrical verification of the circuit layout, including verification of whether the layout rules meet the requirements, whether the components are correctly arranged, and whether the layout connections comply with electrical specifications.
3. DRC/LVS inspection: Use software tools such as Design Rule Check (DRC) and Circuit Verification Rule Check (LVS) to check the circuit to ensure that the circuit design complies with the manufacturing specifications and standards of the chip process to avoid manufacturing failures due to design rule violations. .
4. Electromagnetic compatibility inspection: Check the electromagnetic compatibility of the chip, including inspection of the chip's radiation and sensitivity, to ensure that the chip meets electromagnetic compatibility standards and to avoid abnormal operation of the chip due to electromagnetic interference.
5. Thermal analysis inspection: Check the thermal analysis of the chip, including inspection of the chip's power consumption, heat dissipation, etc., to ensure that the chip will not overheat under normal working conditions and to avoid abnormal operation of the chip due to overheating of the chip.
6. Simulation verification: Conduct simulation verification on the chip, including logic simulation, timing simulation and other aspects to ensure that the chip design meets the expected requirements and avoid abnormal operation of the chip due to design defects.
51. Which of the following factors are related to standard unit dynamic power consumption? ( )
A. Operating frequency
B. Operating voltage
C. Sub-threshold leakage current
D. Output load
Answer: A,B,D
The dynamic power consumption formula is:
Option D affects the capacitor C in the formula.
52. The correct description of 16-point FFT is ( )
A. There are 4 levels of decomposition;
B. Each level has 8 butterfly algorithms;
C. Each butterfly algorithm requires 1 complex multiplication;
D. Each butterfly algorithm requires 1 complex addition;
Answer: A,B,C.
FFT features:
1. There are total 
levels of operation, 16-point FFT is 4 levels of operation.
2. Each level has N/2 butterfly operations.
3. Each butterfly requires one complex multiplication and two complex additions.
53. Which of the following activities can be guaranteed by formal verification ( )
A. Consistency between RTL and RTL
B. Functional integrity of RTL
C. Consistency between RTL and comprehensive netlist
D. Consistency between two different netlists
Answer: A,C,D.
Goals of formal verification:
1. RTL and RTL: Confirm whether the new RTL is functionally consistent with the original RTL.
2. Gate-level netlist and RTL: Make sure the logic of DC synthesis is correct.
3. Between two gate-level netlists: Confirm layout input information and layout output information.
54. According to the constraint relationship set_clock_groups -async -group{CLK1}{CLK2CLK3}, which paths in the figure below will undergo timing checks
A、Path1
B、Path2
C、Path3
D、Path4
Answer: A,C,D.
The set_clock_groups command disables timing analysis between identified clock groups but not between clocks within the same group.
-asynchronous means that the two clock groups are asynchronous and have no fixed phase relationship.
-group Group clocks.
The meaning of this constraint is that clock group {CLK1} and clock group {CLK2 CLK3} are asynchronous.
So signals spanning these two clock domains do not need to be checked.
Reference blog: FPGA timing constraint learning (1)-How to constrain the clock_lu-ming.xyz's blog-CSDN blog
55. With the advancement of IC circuit design technology, the proportion of leakage power consumption is increasing. Regardless of the impact of temperature drift, which of the following technologies can be used to reduce leakage power consumption? ( )
A. clockgating (clock gating)
B. DVFS (dynamic voltage and frequency adjustment)
C. power gating (power gating)
D. DFS (dynamic frequency adjustment)
Answer: B,C. Leakage power consumption is mainly related to voltage.
56. In SOC verification applications, which of the following options are characteristics of the Emulator (simulation accelerator) ( )
A. Higher frequency than FPGA-based prototype verification platform
B. Accelerate software development and reduce verification cycle
C. System-level verification, simulate real scenarios
D. Support post-simulation with timing
Answer: A,B,C,D. Emulator is specially designed to accelerate verification. Compared with FPGA-based prototype verification platforms, Emulator has faster simulation speed and can verify designs faster. Emulator can support larger-scale designs and accelerate the verification of large-scale designs, while the scale of FPGA-based prototype verification platforms is limited by the size of FPGA. Supports simulation with timing.
57. Assume that in a certain SoC environment, there is a UART controller. After linking it to the host and opening the serial port tool for connection, assuming that all hardware circuit faults have been eliminated, then the following statement is correct:
A. Assuming that the characters displayed on the terminal are all garbled, it is likely that the baud rate setting is incorrect.
B. Assuming that there is no display, it is likely that the code has not initialized the UART controller
. C. Assume that the serial port output is normal, but If the input characters cannot be received, it is likely that the interrupt signal of the UART is not connected correctly.
D. Assuming that the output of the UART is completely normal, but the input characters cannot be received, it is likely that the correct baud rate is not set.
Answer: A,B,C. Option D, the output is completely normal and the baud rate problem can be ruled out.
58. Which are the basic steps about logic synthesis?
A. Translate
B. Mapping
C. Optimization
D. Over Constraint
Answer: A,B,C.
Synopsys synthesis tool DC processing flow: synthesis=translation+mapping+optimization
translation: Convert the HDL description of the design into a logic circuit composed of GTECH library components; the GTECH library is a universal, process-independent component library provided by Synopsys.
Mapping: Map GTECH library components to a specific semiconductor process library. At this time, the circuit netlist contains relevant process parameters.
optimization: the process of further optimizing the circuit netlist based on comprehensive constraints such as delay, area, and line load models set by the designer.
59. Which of the following methods could reduce power consumption for a chip? ( )
A. Use higher advanced process
B. Shut down some useless logic modules
C. Raise voltage
D. Lower frequency
Answer: A,B,D.
Option A, the more advanced the chip process, the lower the supply voltage produces lower dynamic power consumption. Option B, shut down some logic, and both dynamic and static power consumption will be reduced. Option C will increase static power consumption. Option D will reduce dynamic power consumption. Choose ABD.
60.How to fix hold violation in ECO stage?( )
A. Insert delay cells
B. Sizing up cells
C. Add delay in capture clock tree
D. Add delay in launch clock tree
Answer: A,D.
ECO (Engineering Change Order) is a stage in chip design, usually late in the design process. The purpose of this stage is to solve various problems such as power consumption, timing, signal integrity, capacity, etc. by modifying the design. The process of ECO usually involves modifying the logic, physical layout, etc. of the circuit to meet the design requirements.
Option A, inserting buffer can repair hold violation. Option B, Sizing up cells refers to modifying the size of the transistor, which will not play a big role in repairing the hold violation. Option C, delay should be added on the launch side.
61. ESD (Electrostatic discharge) is the sudden flow of electricity between two electrically charged objects cansed by contact, an electrical short, or dielectric breakdown. What are the ESD cases in daily life?( )
A. The static electricity you can feel after drying clothes in a tumble dryer
B. Rub a carpet and then touch a metal door handle
C. Touch a metal stick with anti-static gloves
D. The shock when touching the banister of an escalator
Answer: A,B,D.
Examples of ESD (Electrostatic discharge) in daily life:
A: The static electricity you can feel after drying clothes in a tumble dryer
B: Rub the carpet and then touch the metal door handle
C: Use anti-static gloves to touch metal rods
D: Click when touching the escalator handrail
62. Dynamic power is proportional to( )
A. Frequency
B. Load Capacitance
C. Work temperature
D. Threshold Voltage
Answer: A,B.
63. Which of the following descriptions is correct about inverter?( )
A. CMOS inverter VTH is about 1/2VDD
B. When input is low, the output voltage=VDD
C. Inv is an important device for Memory
D. We want smaller SNM in the circuit
Answer: A,B.
Latch and FF are very important to Memory and have nothing to do with inverter. SNM is the static noise margin. The larger the SNM, the better the anti-interference performance of the circuit.
64.What are the characteristics of PN junction?
A. One-way conductivity
B. Capacitance characteristics
C. Resistance characteristics
D. Breakdown characteristics
Answer: A,B,D.
65. What are the levels of PC protocol?
A. Transaction Layer
B. Data Link Layer
C. Physical Layer
D. Network Layer
Answer: A,B,C.
PC (Peripheral Component Interconnect) is a commonly used computer bus standard. Its protocol level includes the following four parts:
1. Physical Layer: Mainly responsible for the physical part of transmitting data, including bus width, clock frequency, transmission rate and other hardware-related details.
2. Data Link Layer: Responsible for data transmission, flow control, error detection and correction and other functions to ensure data reliability.
3. Transaction Layer: Responsible for managing operations such as data transmission, caching and retransmission, and handling the relationship between multiple data transmission requests and responses.
4. Application Layer: Provides a series of access and control interfaces for upper-layer software to realize functions such as data transmission, storage and processing.
66.which of following code would print “hello”( )
A.
int main(){
int num= 100;
char*p= NUL;
char str[]="hello";
num= strcpy (p,str);
printf ("%s\n", str);
return 0;
}
B.
int main(){
char*p=NULL;
char str[]="hello";
sprintf (p,str);
printf ("%s\n"，p);
return 0;
}
C.int main() {
int num=100;
char*p=(char*)malloc(20);
char str[]="hello";
num=strcmp(p,str);
printf ("%s\n", p);
free(p);
return 0;
}
D.
int main(){
char*p=(char*)malloc(20);
char str[]="hello";
sprintf (p,str);
print("%s\n", p);
free(p);
return 0;
}A. A
B. B
C. C
D. D
Answer: A,D.
In C language, the sprintf() function is used to write formatted data into a string. Its syntax is as follows
int sprintf(char *str, const char *format, ...)Among them, the first parameter is a pointer to the target string, the second parameter is the format string, and the following parameters are the data to be formatted for output. The sprintf() function returns the number of characters written to a string.
For example:
#include <stdio.h>
int main()
{
char str[100];
int num = 123;
float f = 3.14159;
sprintf(str, "The number is %d and the float is %f", num, f);
printf("%s\n", str);
return 0;
}The output is:
The number is 123 and the float is 3.141590A：strcpy：char *strcpy(char *dst, const char *src);
Here str is copied to p, but str is eventually output.
B:sprintf: int sprintf( char *buffer, const char *format [, argument,…] );
Formatted output characters to another string.
The pointer here does not point to the opened space.
C: The strcmp() function is used to compare two strings (case sensitive).
int strcmp(const char* stri1，const char* str2);
67. Among the following statements about verilog, which one is correct: ( )
A. In the always block that describes combinational logic, you can avoid synthesizing the latch by assigning an initial value to the variable at the beginning. B. The
generate statement can be used to instantiate a module multiple times
. C. Used for synthesis In the code, the assignment to the same register can appear in two always blocks.
D. systemverilog is a language used for verification, so it cannot be synthesized.
E. Constants such as the state encoding of the state machine are generally defined with parameters.
Answer: ABE.
68. The following methods can be used to eliminate the risk of competition in circuits: ( )
A. Connect a small filter capacitor to the combinational logic output
B. Modify the logic design
C. Introduce strobe pulses
D. Add redundant items to the design
Answer: BCD. Option A is not a solution to competing risks, but is used to smooth out jitter in digital signals.
69. Among the following statements about metastable state, which one is correct: ( )
A. Transmission of data across clock domains will definitely lead to metastability.
B. Setup time or hold time violations in sequential circuits will lead to metastability.
C. When a register is metastable, its output cannot be determined until it is finally stable. terminal is logic high or logic low
D. If the metastable state is not processed, erroneous data or metastable flags may be propagated in the circuit and the conductor chip function may be incorrect.
Answer: BCD.
70. Which of the following statements is wrong: ( )
A. The decimal number corresponding to (10101.001)2 is 15.125
B. In the remainder code, the sum of 0110 and 1000 is 1110
C. The results of Huffman encoding are all equal-length codewords
D. In the BCD code , the result of 5+7 is 1100
Answer: ACD.
A. The decimal number corresponding to (10101.001)2 is (1 × 2^4 + 0 × 2^3 + 1 × 2^2 + 0 × 2^1 + 1 × 2^0 + 0 × 2^-1 + 0 × 2^-2 + 1 × 2^-3)10 = 21+ 0.125 = 21.125. Therefore option A is incorrect.
B. In the remainder code, the complement of 0110 is 1001, and the complement of 1000 is 0111, so the sum of the two is 1110. Therefore option B is correct.
C. The result of Huffman coding is codewords of unequal lengths, which are often used in fields such as data compression. Therefore option C is incorrect.
D. In the BCD code, 5 is represented as 0101 in binary, and 7 is represented as 0111 in binary. Add them to get (0001)BCD, that is, 0001 + 0101 + 0111 = 1101BCD, so option D is wrong.
71. Among the following statements about FIFO, which one is correct: ( )
A. The conversion circuit from Gray code to binary code in the asynchronous FIFO is to generate the address for accessing the memory.
B. When the read and write clock frequencies are the same, the read and write addresses do not need to be encoded with Gray code.
C. The "virtual full" cry caused by crossing the clock domain "Void" will not cause functional errors
D. For an asynchronous FIFO with a depth of 32, the read address pointer requires 5 bits
E. The synchronous FIFO will not overflow because the read and write clocks are the same
Answer: ACD. Option B is wrong. Gray code is used to solve the metastability problem. Option E is wrong. The read and write clocks are the same, which does not mean the read and write rates are the same.
72. Which of the following statements is wrong: ( )
A. Push-pull output needs to be set with a pull-up resistor
B. Open-drain output needs to be set with a pull-up resistor
C. Open-drain output can be used for wired AND implementation
D. Push-pull output cannot output a true low level
Answer: AD.
Reference blog: Push-pull output && open-drain output_Push-pull output and open-drain output_Xiangzaifei's blog-CSDN blog
73.The delay of a designed standard unit of CMOS logic circuit mainly depends on which of the following factors? ( )
A、Input transition
B、Output transition
C、Input load
D、Output load
Answer: ACD.
Option A, Input transition, is the rise time and fall time of the input signal. The faster the input signal changes, the greater the delay is usually.
Option C, Input load, is the input load, which is the capacitive load connected to the input port. The larger the load, the greater the delay.
Option D, Output load, is the output load, which is the capacitive load connected to the output port. The larger the load, the greater the delay.
74. If there is a hold violation on the timing path to a certain register, which of the following methods can fix the violation? ( )
A. Add a buffer to the data end of the register to increase the data delay.
B. Add a buffer to the clock end of the register to increase the clock delay.
C. Add a buffer to the clock end of the previous stage register to increase the clock delay of the previous stage register. Delay
D. Add a latch between this register and the previous register.
Answer: AC. Let the data of this register arrive slowly, and the clock of the previous register arrive slowly.
75. Which of the following C language declaration statements is correct ( )
extern int *x;
extern int y[];
A. The first statement declares that x is a pointer of type int
B. The first statement declares that x is a data of type int
C. The second statement declares that y is an array of type int with an undetermined length
D. The second statement declares y It is an int type array with a certain length.
Answer: AC.
76.What are the characteristics of virtual sequencer in UVM ( )
A. The virtual sequencer controls other sequencers.
B. The virtual sequencer is not connected to any driver
. C. The virtual sequencer does not process items
. D. The virtual sequencer mainly coordinates the execution of different sequences.
Answer: ABCD.
Reference blog: UVM basics-Sequence, Sequencer (2)_uvm sequencer_The blog of pickled fish that does not eat onions-CSDN blog
77. Which of the following descriptions of verilog functions and tasks is correct ( )
A. Delay control can be added to the Function structure
. B. Delay control can be added to the Task structure
. C. Task can be called in the Function
structure. D. Function can be called in the Task structure.
Answer: BD. The difference between function and task
task：
A task can call another task or another function;
a task can be executed at a non-zero simulation time;
a task can contain delay, time or timing control declaration statements;
a task can have no or multiple inputs (inputs) and outputs (outputs) ) and bidirectional (inout) variables;
tasks do not return any values, and tasks can pass multiple values through output (output) or bidirectional (inout) variables; task
calls are implemented through a separate task call statement;
task calls can only occur In a procedure block;
task execution can be interrupted by the disable statement.
function：
A function can call another function, but not another task;
the function always starts execution at simulation time 0;
the function must not contain any delays, events, or timing control declarations;
the function has at least one output variable, and can have multiple Input variables;
functions can only return one value, and functions cannot have output (output) or bidirectional (inout) variables; functions cannot
appear as a separate statement, they can only appear as part of a statement;
function calls can appear in procedures In block or continuous assignment statements;
the execution of the function is not allowed to be interrupted by the disable statement.
78. Regarding cross-clock processing, which of the following descriptions is correct ( )
A. When a single-bit signal is synchronized across clocks, you can directly use the target clock for 2 beats.
B. When a multi-bit signal is synchronized across clocks, you can directly use the target clock for 2 beats.
C. When synchronizing the asynchronous FIFO read and write pointers, you need to use Gray code
D. Synchronization FIFO read and write pointers do not need to use Gray code when passing each other
Answer: ACD.
79.Which of the following ways can the C language in systemverilog access the signals in the DUT? ( )
A、PLI
B、VPI
C、DPI
D、force或deposit
Answer: ABC.
Option A, PLI (Programming Language Interface): The PLI interface is similar to VPI. You can also read and write variables in SystemVerilog or call functions in SystemVerilog in C/C++ code. However, the PLI interface is part of the Verilog language and can only be used in the Verilog compiler. The PLI interface provides a series of callback functions that can be used to access and operate various objects in Verilog.
Option B, VPI (Verilog Programming Interface): The VPI interface is similar to DPI. You can read and write variables in SystemVerilog or call functions in SystemVerilog in C/C++ code. VPI is an object-oriented interface that provides a series of functions and callback functions that can be used to access and operate various objects in SystemVerilog.
Option C, DPI (Direct Programming Interface): Use DPI to integrate SystemVerilog with C/C++ code. Through the DPI interface, you can directly read and write variables in SystemVerilog or call functions in SystemVerilog in C/C++ code.
80. Regarding the difference between synchronous reset and asynchronous reset, which of the following statements is correct ( )
A. Synchronous reset judges the reset condition at the edge of the clock and completes the reset action.
B. Asynchronous reset completes the reset action regardless of the time status as long as the reset condition is established.
C. Asynchronous reset signals are generally released synchronously.
D. Synchronous reset signals do not allow glitches.
Answer: ABCD. Both synchronous reset and asynchronous reset should be released synchronously to avoid metastability.
81. Which of the following factors are related to dynamic power consumption in CMOS chip design ( )
A. Voltage
B, frequency
C, resistance
D, load capacitance
E, process
F, operating temperature
Answer: ABD. Considering dynamic power consumption, the dynamic power consumption formula is 1/2V^2Cf, and ABD can be determined according to the formula. It is uncertain whether option E process is selected.
82. Related to FPGA global clock resources are ( )
A、BUFG
B、DCM
C、NOT
D、DFF
Answer: ABD. BUFG (Buffered Universal Global Buffer) and DCM (Digital Clock Manager) are two important components related to FPGA global clock resources. BUFG is a special clock buffer that can transmit the clock signal from the edge of the FPGA device to any location inside the FPGA device and ensure that the delay and jitter of the clock signal are kept to a minimum. DCM is a clock manager that can generate clock signals and perform operations such as phase offset, frequency adjustment, clock multiplication and frequency division on the clock signals.
NOT is a logical NOT gate and has nothing to do with the clock. DFF latches data through global clock control.
83. The following are dual-state data types ( )
A、byte
B、logic
C、bit
D、integer
Answer: AC.
84. Which of the following factors need to be considered when calculating clock delay in static timing analysis ( )
A. Clock source jitter (jitter)
B. Register setup and hold time
C. Deviation (skew) introduced by clock tree imbalance
D. On-chip variation caused by process characteristics
Answer: ACD. Calculating the delay of the clock has nothing to do with the register. Pay attention to the question review.
85. The following logic (A, B, D) can be realized: input three 1bit A, B, C variables, if more than two of them are 1, then output 1:
A、x=（A&B）|（B&C）|（C&A）
B、x=（~A&B|~B&A）^C
C、x=（~A&B|~B&A）?C：A
D、x=（~A&B|~B&A）?C：B
Answer: ACD. Special value method.
86. Which of the following verilog descriptions will generate registers ( )
A、always@（clk）
reg_a<=reg_b；
B、always@（negedge clk）
reg_a<= reg_b；
C、always@（posedge clk）
reg_a<=reg_b；
D、assign reg_a=reg_b；
Answer: B.C. Only BC is clock edge triggered.
87. How to solve the problem of unsatisfied setup timing of a critical path without increasing the pipeline? ( )
A. Move some combinational logic circuits to the front-end path
B. Use a more advanced technology library
C. Reduce the clock frequency
D. Insert registers on this path
Answer: ABC. Option D inserts a register to add to the pipeline.
88. Regarding overloading, the following descriptions are correct ( )
A. Functions and tasks can be overloaded
B. Transaction can be overloaded
C. Sequence cannot be overloaded
D. Overloading of the UVM factory mechanism requires that the overloaded class must be derived from the overloaded class
Answer: ABD. sequence can be overloaded. In UVM, overloading refers to defining functions, tasks, tasks, methods, etc. with the same name but different parameter types and numbers in the same scope. Through overloading, the reusability and flexibility of the code can be improved, while making the code more readable and understandable.
89. An effective method to improve metastability problems is ( )
A. Introduce a synchronization mechanism, such as adding a two-stage flip-flop
B. Reduce the clock frequency
C. Improve the clock quality and use a clock signal with fast edge changes
D. Use a DFF with a faster response
Answer: ABCD
90.The correct description of virtual sequencer is ( )
A. The virtual sequencer is not connected to any driver
. B. The virtual sequencer can control other sequences
. C. The sequence is not generated and transmitted in the virtual sequencer
. D. The virtual sequencer itself can transmit transactions.
Answer: ABC.
Reference blog: UVM basics-Sequence, Sequencer (2)_uvm sequencer_The blog of pickled fish that does not eat onions-CSDN blog
91.Which of the following classes are derived from uvm_component()
A、Sequencer
B、Monitor
C、Transaction
D、Driver
Answer: ABD
92. Regarding threads, the following description is correct ( )
A. The disable statement can terminate all threads in advance
. B. fork...join, fork...join_none, and fork...join_any statement blocks are executed in a concurrent manner.
C. Any statement block inside fork...join_none is executed. After completion, the parent thread can continue to execute
D, fork...join_any. After all statement blocks inside join_any are executed, the parent thread can continue to execute.
Answer: AB.
93. Given the regular expression /^[0-5]? [0-9]$/, the string that meets this matching condition is ()
A.9
B.10
C.00009
D.999
E.99
Answer: The meaning of this regular rule is to match the beginning of the line [0-5] zero or once, and match the end of the line [0-9] once. The one that meets the requirements is AB. Option C is wrongly repeated at 0 more than once.
94. Which correlations in the processor can cause pipeline conflicts ()
A. Data related
B. Result related
C. Instruction related
D. Resource related
E. Control related
Answer: ADE
Pipeline conflict is a phenomenon that occurs in the CPU pipeline. It is usually caused by certain instructions that depend on previous instructions during execution or because of data dependencies. The following related situations in the processor may cause pipeline conflicts:
-
Data dependency: Data dependency occurs when one instruction requires the operation result of another instruction. If there is insufficient time between these two instructions, data-related pipeline conflicts will result.
-
Resource dependency: When multiple instructions need to use the same component, such as ALU, registers, etc., resource dependency will occur. If these instructions need to access these components during the same clock cycle, this can lead to resource-related pipeline conflicts.
-
Control dependency: Control dependence occurs when an instruction needs to change the value of the program counter (PC). In this case, the processor must wait for the previous instruction to complete before determining the address of the next instruction, thus causing a pipeline conflict.
There are also some optimization technologies in the processor, such as predicted branches, superscalar execution, etc., which can reduce the occurrence of pipeline conflicts. However, these techniques cannot completely eliminate pipeline conflicts, so when writing a program, it is necessary to reduce dependencies as much as possible to improve the execution efficiency of the program.
95. The following errors regarding cache write hit handling are ()
A. Store the data directly into the main memory and no longer load it into the cache.
B. Swap out the storage row with the least number of accesses and clear the row counter.
C. Do not modify the main memory directly, only modify the cache and set dirty bit to mark whether the data has been modified
D. Write the data to the Cache and main memory at the same time, using the write buffer
Answer: ABD.
Option C is correct. It does not modify the main memory directly. It only changes the Cache, sets the dirty bit, and marks whether the data has been modified.
When the processor accesses the Cache, if the data already exists in the Cache, that is, a cache write hit occurs, the processor does not need to access the main memory again and can directly read and modify the data in the Cache. However, in order to ensure data consistency, when modifying data in the Cache, the dirty bit needs to be set, indicating that the data has been modified, and the modified data is stored in the Cache instead of directly modifying the data in the main memory.
Option A is incorrect because storing data directly into main memory will cause data in Cache and main memory to be inconsistent.
Option B is also incorrect because the storage row that has been accessed the least often does not necessarily contain the data to be modified, and swapping out this row has no impact on data consistency.
Option D is also incorrect because the data in the write buffer is not written to main memory and cache, which may cause data inconsistency. Write buffering is primarily used to optimize the speed of write operations.
96.Which descriptions are correct for System-Verilog language?( )
A. Inheritance
B. Classed based OOP
C. Prototype -based OOP
D. Polymorphism
E. Encapsulation
Answer: ABDE.
SystemVerilog is similar to C++ and is class-based and object-oriented. Prototype-based is typically JavaScript.
Three characteristics of SystemVerilog object-oriented:
-
Encapsulation
-
Inheritance
-
PolymorphismPolymorphism
97.Memory BIST can test below elements in the design. ( )
A. Address decoder
B. Memory Array
C. ECC(Error Check & Correct) logic
D. Memory access control logic
Answer:. DFT knowledge, not sure.
98.Select the items which could contribute to functional coverage? ( )
A. SV Cover groups
B. SV Assert Property
C. PSL
D. SV Cover Property
Answer: ABD.
Option A. SV Coverage Group: Coverage groups are used to group coverage items and track their coverage in simulation. By using coverage groups, you can specify coverage targets for your design.
Option B. SV Assertion Attributes: Assertions can be used to verify that a design meets certain functional requirements. By adding assertions in the testbench, you can check that the design is running correctly.
Option C. PSL: PSL (Property Specification Language) is a language used to specify the properties that a design must satisfy. You can use PSL to check whether a design meets certain functional requirements.
Option D. SV Coverage Properties: Coverage properties are used to specify coverage targets for the design. By using the coverage property, you can track coverage of specific signals or events in your design.
99.Which are the main components of a testbench? ( )
A. Monitor
B. Checker
C. Scoreboard
D. Reference model
E. FIFO
Answer: ABCD.
Reference blog: Build a simple UVM verification platform from scratch (1)_The blog of pickled fish that does not eat onions-CSDN blog
100.We need to define clock specifications in SDC file, using commands like below:
Create_clock -name GFXCLK -period 600 -waveform {0 300 }
what can we know from this command? ( )
A. Clock frequency
B. Clock duty cycle
C. Clock source latency
D. Clock name
Answer: ABD.
-name: Specify a string as the clock name.
-period: Define the clock period.
-waveform: duty cycle of the clock signal. {rising edge time, falling edge time}
101.Which ways are efficient for cross talk fix?( )
A. Use wide net
B. upsize driving cell
C. add keep out margin
D. downsize driving cell
Answer: ACD.
-
Use wide lines: One way to reduce cross-interference is to use wider lines between the affected signals. Wider lines create more distance, reducing the potential for interference.
-
Add a retention gap: A retention gap is an empty space surrounding a critical component or sensitive signal. Adding a preservation gap around a sensitive signal prevents other signals from interfering with it.
-
Reduce the size of the driver unit: In some cases, the driver unit may be too large and too powerful, interfering with the signal. In this case, cross interference can be reduced by reducing the signal strength by reducing the size of the driver unit.
102.How to fix the EM problem on signal net?
A. set non default rule for violation signal net, increase wire width
B. set non default rule for violation signal net, decrease wire width
C. decrease the signal net fanout
D. increase the signal net output load
Answer: ACD
A. Set non-default rules for offending signal nets: This may involve changing spacing rules between signal traces, adjusting the size or location of vias, or adding ground planes or shielding. Increase the wire width: This may help reduce the current density in the wire, reducing electromagnetic problems. However, increasing wire width may increase capacitance and signal delay, requiring a balancing trade-off.
Option C. Reduce signal network fan-out: This may help reduce the amount of current flowing in the signal network, thereby reducing electromagnetic problems. However, reducing fanout may also impact the performance and functionality of the design.
Option D. Increase signal network output loading: This may help reduce peak currents in the signal network and mitigate electromagnetic issues. However, increasing the output loading may also affect the circuit's power consumption and signal integrity.
103.Which solutions can be used to reduce parasitic for critical net? ( )
A. Reducing Interconnect Resistance
B. Increasing Wire Spacing
C. Reducing parasitic for Correlated Nets
D. Routing in lower (thinner) metals
Answer: ABC. Option D, using thinner metal will increase interconnect resistance and increase parasitic effects.
-
Reduce interconnect resistance: Reduce the resistance of the line by using wider metal lines or increasing the thickness of the metal layer, thereby reducing parasitic effects.
-
Increase line spacing: By increasing the distance between lines, you can reduce the capacitance between lines, thereby reducing the effects of crosstalk.
-
Use shielding technology: Shielding technology, such as metal shielding, impedance matching, etc., can be used near critical networks to reduce the impact of noise and interference.
-
Optimize layout: Proper layout can reduce the length and complexity of signal paths, thereby reducing the impact of parasitic effects.
104. Please determine which of the following circuits are sequential logic circuits ()
A. Counter
B. Register
C. Decoder
D. Flip-flop
Answer: ABD.
To determine whether a device belongs to a sequential logic circuit, you can consider the following aspects:
-
The role of the device: Sequential logic circuits are usually used in applications that require time considerations such as storage, control, and counting . If the device's role is relevant to these applications, it may be a sequential logic circuit.
-
Input and output characteristics of the device: The output result of the sequential logic circuit is affected by the time sequence and status of the input signal. Therefore, the input and output characteristics of the device can also be an important basis for judging whether it belongs to a sequential logic circuit.
-
Internal structure of the device: Sequential logic circuits are usually composed of flip-flops, counters, state machines, etc. These devices have internal storage devices, clock signal control and other structures. Therefore, you can determine whether it belongs to sequential logic by analyzing the internal structure of the device. circuit.
If the function of a device is related to applications that require time considerations such as storage, control, and counting, and it has the characteristics of a sequential logic circuit, such as an internal structure with storage devices, clock signal control, etc., then the device can be judged to belong to a sequential logic circuit. .
105.Which of the following descriptions is true of digital signals（）
A. It is a discrete signal in time, but it cannot be a discrete signal numerically
B. The signal is discontinuous in time and always occurs in a sequence of discrete moments
C. Numerically quantized, can only be evaluated by a finite number of increments or steps
D. It is a continuous signal in time, and it must be a discrete signal numerically
Answer: B.C. Option A, digital signals are discrete signals in both time and value. Option B, the signal is discontinuous in time and always occurs in a series of discrete moments (edge trigger, level trigger). Option C is correct. Digital signals represent continuous variables and require approximation. For example, digital signals are used to represent the function sinx, and discrete x values are obtained, calculated, and stored in tables. Option D, the signal is obviously wrong continuously in time.
106.What are commonly used techniques to reduce dynamic power in low power design?
Pick ONE OR MORE options
A. Bus signal encoding, bus decoding (5 points)
B. Clock gating
C. Power gating
D. Dynamic voltage and frequency scaling(DVFS)
E. Body biasing
Answer: ABCDE. Option A, bus signal encoding, can reduce the number of signal changes on the bus, thereby reducing dynamic power consumption.
Option E, Body biasing is a technique used in digital circuits to optimize circuit performance and power consumption. It can adjust the speed and power consumption of the circuit by changing the threshold voltage of the transistor to adjust the voltage at which it turns on and off. Body biasing can make the transistor work near its optimal operating point, thereby reducing the switching delay of the transistor, and reducing the energy consumption of the transistor during switching, thereby reducing dynamic power consumption. In addition, by adjusting the threshold voltage of the transistor, the saturation current and leakage current of the transistor can be changed, thereby reducing static power consumption. This can also be achieved through body biasing.
107. Regarding the Pipeline used in the design, the correct statements are:
A. Using Pipeline will cause data delay to increase, but if the operating frequency remains unchanged, the system throughput will not change.
B. Using Pipeline will be good for timing, and STA will pass more easily.
C. Using Pipeline can definitely reduce the area.
D. Using Pipeline may cause the area to increase.
Answer: ABD.
Using pipeline may increase the area. If the original combinational logic depth is deep, in order to achieve the target operating frequency, the synthesis will use a high-thrust cell, or use a special circuit structure (for example, the adder uses a carry-lookahead adder). At this time, the pipeline is cut, reducing the number of steps at each stage. Combinational logic depth, although the number of registers is increased, the number of cells in the combinational logic may decrease; if the depth of combinational logic is not that extreme, the number of registers increased after cutting the pipeline will actually increase the area.
108.Which of the following designs may have an adverse impact on chip DFT?
A. Gated clock design
B. Using double-edge clock design
C. Internal three-state gate bus
D. Using internally generated clock
Answer: ABD.
Option A. Gated clock edges may affect test pattern injection and scan chain progression.
Option B. There may be unknown or uncontrollable states in the scan chain.
Option C. The internal tri-state gate bus does not necessarily adversely affect DFT testing, as it enables the injection of scan chains and test patterns.
Option D. Using an internally generated clock may not synchronize with the clock injected in test mode, causing the test to fail.
109. Which of the following expressions can be implemented using one or more two-input NAND gate devices?
A.Constant 1
B. A
C. A+B
D. AB
Answer: ABCD.
110. Multi-bit signal A, during the change process from 8'd100 to 8'd101 in the clock domain clk_a, if the D flip-flop is directly sampled in the clock domain clk_b, the sampled data may be
A.8'h65
B.8'b01100101
C.8'h64
D.8'd100
Answer: ABCD. Only one bit of the data line has changed, the other bits will not have metastable problems, they may be 8'd101 or 8'd100
111.Formality is a formal verification (Formal Verification) tool developed by Synopsys, used for equivalence verification between two Designs. Which of the following equivalence verifications can it support?
A Gate-level netlist versus gate-level netlist
B. RTL-level versus RTL-level
C. RTL-level versus gate-level netlist
Answer: ABC.
112.
①: always @(posedge clk or negedge rst_n) begin
if(!rst_n)
din_dly <='h0;
else
din_dly <= din;
end
②: always @(posedge clk) begin
din_dly <= din;
end
③: always @(posedge clk) begin
if(!rst_n)
din_dly <= 'h0;
else
din_dly <= din;
endThe above three pieces of code are correct:
A. ② It belongs to a non-reset register, and its PPA is better.
B. ① It belongs to asynchronous reset logic
. C. Both synchronous reset and asynchronous reset initialize the register state during reset, so there is no difference.
D. ③ It belongs to synchronous reset logic, and rst_n may pass The combinational logic is connected to the D terminal of the register.
Answer: ABD.
113. The differences between FPGA and ASIC chip design need to be paid attention to:
A. Clock reset
B. Clock frame rate
C. Memory control
D. Power on and off process
Answer: ABCD. Everyone should pay attention
114. Message processing design specifications:
The supported packet length is 36-256 bytes, and packets with other lengths are directly discarded;
When the length of the received message is less than 64 bytes, pad PAD (arbitrary data) to make the message length reach 64 bytes, and then forward it; the following errors are described:
A. Because PAD is filled with arbitrary data, you can pick a set of special values at random. For example, all-0 verification can ensure correct function. B.
Because messages larger than 256B are discarded, there is no need to verify this point
. C. Because messages smaller than 36B The packet was discarded, so there is no need to verify point
D. The boundary point of the packet processing length contains two values, 36 and 256 respectively.
Answer: ABC. The spec says that the packets are discarded, but you are not sure whether the design actually discards the packets and needs to be verified.
115. Which of the following are necessary during Post-Layout timing simulation?
A.Post-Layout netlist
B. Comprehensive netlist
C. Standard delay format file
D.RTL code
Answer: AC. When performing Post-Layout timing simulation, you must have a Post-Layout netlist and a standard delay format file, because these two files contain physical information and timing information and can provide more accurate simulation results than a comprehensive netlist.
116. When the code coverage of a module reaches 100%, which of the following statements is incorrect?
A. It cannot ensure that the verification work has been completed.
B. It can confirm that the incentive structure of various use cases has been completed
. C. It can confirm that the testing of various boundary points has been sufficient.
D. It can confirm that the functional verification has been sufficient.
Answer: BCD.
117.In System Verilog, the wrong description of the logic type is
A. The initial value of logic is 'x'
B. Logic can completely replace the wire type
C. Logic can completely replace the reg type
D. The logic type is four-valued logic
Answer: B.C. The initial value of logic is x. logic is four-valued logic.
118.Fuse selection is mainly based on which of the following parameter values are comprehensively considered ()
A.Hot melt value
B. Breaking current
C. Rated voltage
D. Rated current
Answer: ABCD. Fuse is a fuse, A: The thermal melt value is the heat required when the fuse is blown; B Breaking current: The maximum current that the fuse can withstand at the specified voltage before breaking.
119. Among the following sorting algorithms, which time complexity will not exceed nlogn? ()
A. Merge sort
B. Bubble sort
C. Quick sort
D. Heap sort
Answer: ACD. The time and space complexity of the sorting algorithm are shown in the figure below.
