Reordering the CPU and MESI cache coherency

A, reorder scenes

class ResortDemo {
    int a = 0;
    boolean flag = false;

    public void writer() {
        a = 1;                   //1
        flag = true;             //2
    }

    Public void reader() {
        if (flag) {                //3
            int i =  a * a;        //4
            ……
        }
    }
}  

When the two threads A and B, A first executes writer () method, then thread B then performs Reader () method. Thread B 4 while performing the operation, the ability to see one pair of shared variables in a thread A write operation?

The answer is: not necessarily see.

Since the operation 1 and operation 2 no data dependencies, the compiler, and the two processors may operate reordering; Similarly, 3 and operation 4 operation no data dependencies, the compiler and the processor may operate the two heavy Sort.

Second, traced

　　In order to enhance computing performance, CPU upgrade from single-core to multicore even use the Hyper-Threading technology to maximize improve the processing performance of the CPU. Increase the CPU cache, the operating system adds processes, threads, by switching the CPU time slice to maximize the usage of CPU upgrade.

 

　　By storing a cache of interaction good solution to the contradiction between the processor and memory speed, but it also brings greater complexity of computer systems, because it introduces a new problem, cache coherency.

 Third, the cache coherency protocol

　　The same data may be cached in multiple CPU, if different threads running in different CPU seen with a cache memory is not the same value will be inconsistent caching problems. In order to achieve consistent data access, each processor needs to follow some protocol when accessing the cache, operate according to the protocol at the time of reading and writing, there is common agreement MSI, MESI, MOSI and so on. The most common is the MESI protocol. 

Next

 

To you briefly explain MESI.

　　MESI cache line represents the four states, namely,

　　1. M (Modify) represents only the shared data cached in the current CPU cache, 

And is a modified state, i.e. the number of data cache and main memory

 It is inconsistent

　　2. E (Exclusive) exclusive state indicates the cache, the data cache only the current 

CPU cache and is not modified

　　3. S (Shared) may be data representing a plurality of CPU cache and main memory, and consistent data for each data cache

　　4. I (Invalid) cache has expired represents

 

　                                            

                                          

 

 

                                                          

　　For MESI protocol, CPU read and write from the point of view will follow the following principles:

　　CPU read request: the cache is M, E, S status may be read, I status of the CPU can only read data from main memory.

　　CPU write request: the cache is in M, E status before they can be written. For the S state of writing, it requires the other CPU cache line invalidated before writing.

 Fourth, the reordering reasons

　　Although MESI cache coherency protocol can be achieved, but also there are some problems.

　　

 

 　　Based on the figure above reasons, CPU and the introduction of a buffer storeBuffers. CPU0 only when writing shared data, write data directly to storebufferes while invalidate message sent, and continue to process its

他指令。当收到其他所有 CPU 发送了 invalidate acknowledge 消息时，再将 store bufferes 中的数据数据存储至 cache line中。最后再从缓存行同步到主内存。        

                                                                  

 

 　　　　这个时候，我们再来看上述标题一中的重排序场景。

　　　　class ResortDemo {
  　　　　  int a = 0;
  　　　　  boolean flag = false;

  　　　　  public void writer() {
  　　　　      a = 1;                   //1
   　　　　     flag = true;             //2
  　　　　  }

　　　　    Public void reader() {
　　　　        if (flag) {                //3
  　　　　          int i =  a * a;        //4
            ……
  　　　　      }
 　　　　   }
　　　　}  

  When performing an operation, the state of A from S-> M, In this case, the thread A is changed will be written to the first storebuffers, then send an asynchronous notification to invalidate other CPU threads, immediately following the implementation of the second operation. 
At this point, you may still change in storebuffers 1, has not been submitted to the main memory. When it will be submitted to the main memory, not sure. 
Therefore, thread B calls the read method may appear, see the flag changes, but can not see a change, and there have been reordered phenomenon.