"Westward processor" MESI Cache coherency protocol of [turn]

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 Cache MESI coherency protocol of
          a complete agreement on the processor to ensure Cache consistency. More classic Cache coherency protocols undoubtedly MESI protocol, the Pentium processor has to use it, many other processor is using its variants.

Mononuclear Cache Cache line each have two flags: dirty and valid flag are well described the relationship between the data (memory) and a Memory Cache (whether valid data, whether the data is modified), and in the multi-processor vessel, multiple cores share some data, the MESI protocol contains the description of the shared state.

         In the MESI protocol, each state has four Cache line, bit 2 indicates available, they are: 

status

description

M(Modified)

This line of data is valid, the data is modified, and inconsistencies in the data memory, data is only present in the Cache.

E(Exclusive)

This line of data is valid, and the same data in memory, data is only present in the Cache.

S(Shared)

This line of data is valid and consistent data in memory, data exists in a lot of Cache.

I(Invalid)

This line of data is invalid.

MESI state

           Cache line M (Modified), and E (Exclusive) state, the data is unique, except that data in the M state is dirty (inconsistent and memory), the state of the data E (consistent and memory) of the Clean .

          Cache line S (Shared) status, and other data of Core Cache shared. Only clean data in order to be more Cache share.

          I (Invalid) indicates that the Cache line is invalid.

 

          Example E state as follows:

 

 

E status

       Only Core 0 access the variable x, its Cache line state E (Exclusive).

 

        Example S state as follows:

 

S state

         3 Core have access to the variables x, their corresponding Cache line is S (Shared) state.

 

         Example I and the M state state as follows:

 

 

The M state I and state

            After Core 0 modify the value of x, the Cache line becomes M (Modified) state, corresponding to other Core Cache line becomes I (Invalid) state.

 

        In the MESI protocol, each of Cache Cache controller not only know their own reading and writing, but also to monitor (snoop) read and write operations of other Cache. Each Cache line state in which the migration among the four states in accordance with the present write operation of the core and the other cores.

       MESI protocol state transition diagram as follows:

 

MESI protocol state transition diagram

        In the figure above, Local Read Cache Reading a value indicating the kernel, Local Write Write kernel represents the present value of the present Cache, Remote Read other value indicating the kernel reads the Cache other, Remote Write showing another kernel values ​​written in other Cache , Cache line arrow indicates the migration of this state, the circular arrow indicates the status unchanged.

        When the data needs to access the kernel is not present in the Cache, and the Cache other backup of this data may be present Cache import data from memory, the data may be imported from other Cache, different processors have different choices . MESI protocol to make themselves more general, these details is not defined, only defines migration between states, the following description assumes present Cache import data from memory.

        Migration between MESI status as follows:

Current state

event

behavior

The next state

I(Invalid)

Local Read

Other Cache If this data is not present in the Cache fetch data from memory, the state becomes Cache Line E;

If there are other Cache this data, and update the status of M, then the data into memory, then the present Cache fetch data from memory, the Cache Cache line 2 are turned into the state S;

If there are other Cache this data, and the state is S or E, according to the present Cache fetch data from memory, Cache Line Cache these are turned into the state S

I / O

Local Write

Fetch data from memory, modify the Cache, the status becomes M;

If there are other Cache this data, and the status is M, will have to update the first data memory;

If there are other Cache this data, the status of other Cache Cache line becomes I

M

Remote Read

Since it is Invalid, the operation of other nuclear nothing to do with it

I

Remote Write

Since it is Invalid, the operation of other nuclear nothing to do with it

I

E(Exclusive)

Local Read

Data taken from the Cache, the status change

E

Local Write

Cache data is modified, the state becomes M

M

Remote Read

Share data and other core, the state becomes S

S

Remote Write

Data is modified, the Cache line is no longer used, the state becomes I

I

S(Shared)

Local Read

Data taken from the Cache, the status change

S

Local Write

Modify the data in the Cache, the status becomes M,

Other nuclear shared Cache line status changes I

M

Remote Read

State unchanged

S

Remote Write

Data is modified, the Cache line is no longer used, the state becomes I

I

M(Modified)

Local Read

Data taken from the Cache, the status change

M

Local Write

Modify data in the Cache status unchanged

M

Remote Read

This line of data is written to memory, so that other use of nuclear energy to the latest data, the state becomes S

S

Remote Write

This line of data is written to memory, the use of nuclear energy to other recent data, since other nuclear modify this line data,

I became state

I

MESI state transition

           AMD Opteron processors MOESI protocol evolved from the use of the MESI, O (Owned) is a body of MESI S and M, represents the present Cache line is modified, and the inconsistent data in memory, although other core may have this copies of parts of the data, the state is S.

         Intel's core i7 MESIF protocol processor uses evolved from the MESI, F. (Forward) evolved from a Share, the Cache line if a Forward state, it can pass data directly to other cores Cache, and then Share can not.
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