CPU for faster code execution. So when reading data from memory, it is not only the part that you want. Instead, read enough bytes to fill the cache line. Depending on the CPU, the cache line size is different. Such as X86 is 32 BYTES, and ALPHA is 64 BYTES. and is always aligned at the 32nd or 64th byte. In this way, when the CPU accesses adjacent data, it does not have to read from memory every time, which improves the speed. Because accessing memory takes much more time than accessing the cache.
However, the era of multi-core development. The situation is not so simple. Consider the following situation.
1. CPU1 reads a byte, and it and its adjacent bytes are read into CPU1's cache.
2. CPU2 does the same job as above. In this way, the caches of CPU1 and CPU2 have the same data.
3. CPU1 modifies that byte, and after being modified, that byte is put back into CPU1's cache line. But this information is not written to RAM.
4. CPU2 accesses the byte, but because CPU1 does not write data into RAM, the data is out of sync.
To solve this problem, chip designers created a rule. When one CPU modifies a byte in a cache line, the other CPUs in the computer are notified and their caches are considered invalid. Therefore, in the above situation, CPU2 finds that the data in its cache is invalid, CPU1 will immediately write its own data back to RAM, and then CPU2 will read the changed data again. As can be seen, cache lines can cause some inconsistencies on multiprocessors.
It can be seen from the above that when designing the data structure, you should try to separate the read-only data from the read-write data, and try to combine the data accessed at the same time. In this way, the CPU can read in the required data at one time.
Reference: http://blog.csdn.net/boyuejiang/article/details/8908335