1. Concept
MESI (Modified Exclusive Shared Or Invalid) is a widely used cache coherency protocol that supports a write-back strategy.
Each cache line in the CPU core uses 2 bits to represent 4 states.
2. State Machine
M (Modified, modified):
The cache line is only cached in the CPU (if there are other CPUs, it will become invalid), and it is modified, and the modified content needs to be written back to the main memory at some point in the future.
After writing back to main memory, it becomes exclusive
E (Exclusive, exclusive):
The cache line is only cached in the CPU cache, and is not modified.
S (Shared, shared):
The cache line may be cached by multiple CPUs, and the data of each cache line is consistent with the main memory.
When one CPU modifies the cache line, the cache line in the other CPU becomes invalid.
I (Invalid, invalid):
The cache is invalid.
After one core modifies the cache line, the cache lines of other cores become invalid.
3. State transition diagram
A. At first, only one CPU core loaded the cache, then the state of the cache line is Exclusive
B. Two new cores are loaded with the same cache, and the status is all switched to Shared
C. The first core modifies the cache, the status becomes Modified, and the other two cores detect a write operation, then the transition changes to the Invalid state
4. Principle
In a multi-core system, each CPU core has its own cache cache, which has involved cache coherence for a long time.
In the MESI model, the controller of each cache not only knows its own read and write operations, but also monitors the read and write operations of other caches.
Each cache changes the current state of the cache line based on its own state and the newly occurring read and write operations.
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