MONTHS
What is MESI?
==> MESI is a cache coherency protocol
Why should there be MESI?
==> In order to coordinate the caches on multiple CPU cores to keep the data consistent
First of all, because the speed of the CPU and the memory do not match, there is a CPU cache. The cache of a modern CPU is generally divided into three levels, L1, L2, and L3. Generally speaking, on a multi-core processor, each CPU core Own L1 and L2 Cache, L3 Cache is shared by all cores. When the CPU reads a certain data, it will first read it from the cache. If the cache read misses, it will load the data from the main memory to the cache. A unit of data in the cache is called a cache line, which is usually 64 bytes. Loading data from the main memory to the cache is not loaded one byte at a time, but one cache line at a time.
MESI is used to ensure data consistency between multiple caches
How MESI works
MESI is a cache coherency protocol based on invalidation and supports write-back. Since the agreement was invented at the University of Illinois, it is also called the Illinois Agreement.
MESI protocol is an Invalidate-based cache coherence protocol, and is one of the most common protocols which support write-back caches.It is also known as Illinois protocol
The 4 acronyms of MESI respectively represent the 4 states of a cache line
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Modified
The cache line only exists in the current cache, not in other caches, and the data of the cache line is inconsistent with the data in the main memory, which is dirty data (dirty)
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Exclusive
The cache line only exists in the current cache, not in other caches, and the data in the cache line is consistent with the data in the main memory and is clean
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Shared
The cache line exists in multiple caches, and the data of the cache line is consistent with the data in the main memory
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Invalid
The cache line is invalid
The MESI protocol is actually a finite state machine (Finite State Machine) model. In this FSM, 4 states are defined, and 2 types of stimuli that cause state transitions are defined. Simply put, MESI is 4 states, plus 2 incentives.
Each cache needs to receive read and write commands from its own CPU, and it also needs to monitor the events that occur on the bus (bus snooping).
The 2 stimuli are as follows
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The first type of stimuli is on the cpu side. The operations issued by a cpu core to its cache include read and write
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PrRd
The processor request to read a cache block
The processor initiates a read request to its cache
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PrWr:
The processor request to write a cache block
The processor initiates a write request to its cache
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The second type of stimuli is on the bus side, events on the bus monitored by the cache controller
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BusRd
Snooped request that indicates there is a read request to a cache block made by another processor
A cache sniffs a read request from another processor on the bus
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BusRdX
Snooped request that indicates there is a write request to a cache block made by another processor which doesn’t have the block
A cache sniffs a write request from another processor on the bus, and the processor's cache itself does not contain this data
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BusUpgr
Snooped request that indicates there is a write request to a cache block made by another processor but that processor already has that cache block resides in its cache
A cache sniffs a write request from another processor on the bus, and the processor's cache itself contains this data
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Flush
Snooped request that indicates that an entire cache block is written back to the main memory by another processor
A cache sniffs that another processor writes a cache block back to main memory
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FlushOpt
Snooped request that indicates that an entire cache block is posted on the bus in order to supply it to another processor (Cache to cache transfer)
A cache sniffs that there is a cache block passing on the bus
The State transitions and the response at a particular state with respect to different inputs are shown as follow
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| Initial State | Operation | Response |
|---|---|---|
| Invalid(I) | PrRd | Issue BusRd to the busother Caches see BusRd and check if they have a non-invalid copy, inform sending cacheState transition to (S)Shared, if other Caches have non-invalid copy.State transition to (E)Exclusive, if none (must ensure all others have reported).If other Caches have copy, one of them sends value, else fetch from Main Memory |
| PrWr | Issue BusRdX signal on the busState transition to (M)Modified in the requestor Cache.If other Caches have copy, they send value, otherwise fetch from Main MemoryIf other Caches have copy, they see BusRdX signal and Invalidate their copies.Write into Cache block modifies the value. | |
| Exclusive(E) | PrRd | No bus transactions generatedState remains the same.Read to the block is a Cache Hit |
| PrWr | No bus transaction generatedState transition from Exclusive to (M)ModifiedWrite to the block is a Cache Hit | |
| Shared(S) | PrRd | No bus transactions generatedState remains the same.Read to the block is a Cache Hit. |
| PrWr | Issues BusUpgr signal on the bus.State transition to (M)Modified.other Caches see BusUpgr and mark their copies of the block as (I)Invalid. | |
| Modified(M) | PrRd | No bus transactions generatedState remains the same.Read to the block is a Cache hit |
| PrWr | No bus transactions generatedState remains the same.Write to the block is a Cache hit. |
| Initial State | Operation | Response |
|---|---|---|
| Invalid(I) | BusRd | No State change. Signal Ignored. |
| BusRdX/BusUpgr | No State change. Signal Ignored | |
| Exclusive(E) | BusRd | Transition to Shared (Since it implies a read taking place in other cache).Put FlushOpt on bus together with contents of block. |
| BusRdX | Transition to Invalid.Put FlushOpt on Bus, together with the data from now-invalidated block. | |
| Shared(S) | BusRd | No State change (other cache performed read on this block, so still shared).May put FlushOpt on bus together with contents of block (design choice, which cache with Shared state does this). |
| BusRdX | Transition to Invalid (cache that sent BusRdX becomes Modified)May put FlushOpt on bus together with contents of block (design choice, which cache with Shared state does this) | |
| Modified(M) | BusRd | Transition to **(S)Shared.**Put FlushOpt on Bus with data. Received by sender of BusRd and Memory Controller, which writes to Main memory. |
| BusRdX | Transition to (I)Invalid.Put FlushOpt on Bus with data. Received by sender of BusRdx and Memory Controller, which writes to Main memory. |
Reference link:
https://en.wikipedia.org/wiki/MESI_protocol