See a compilation of a lot about the program returns to the interrupt processing the return address is special, think about the effect of the original line of action. So, we decided to consolidate their learning under the ARM pipeline.
ARM7 processor 3-stage pipeline to increase the speed of the processor instruction stream, providing 0.9MIPS / MHz instruction processing speed.
PS:
MIPS (Million Instruction Per Second) indicate how many millions of instructions per second. For example 0.9MIPS, it represents nine hundred thousand instructions per second.
MIPS / MHz CPU expressed in per MHz operating speed of how many MIPS can be performed, such as 0.9MIPS / MHz indicates if the CPU runs at a frequency of 1MHz, perform 900,000 instructions per second.
If the CPU at a frequency of 20MHz, can run 18 million instructions per second. MIPS / MHz may well reflect the speed of the CPU.
3-stage pipeline shown above (PC is a program counter), using three pipeline stages, so the instruction executed in three stages.
⑴ fetch an instruction from the load memory
⑵ decode instruction to be executed is identified
⑶ execution processing instruction and writes the result will register
After previously learned 51 single, because relatively simple, so it's processor can only read and execute a complete instruction, will execute the next instruction. In this way, PC is always pointed to "execute" command.
For ARM7 because it is 3-stage pipeline, so the instruction processing is divided into three stages described above.
Therefore, when the actual process is as follows: while the first ARM instruction being executed on the second instruction is decoded, and the third instruction is being fetched from memory.
Therefore, only when the ARM7 pipeline take the first four instructions, the first instruction execution is not complete.
Vividly illustrates the 3-stage pipeline processing mechanism in the figure below
The following is the key word: No matter what state the processor, program counter R15 (PC) always points "are fetch" command, rather than to the instruction "being executed" or is "coding" instruction.
People usually command habit of being executed as a reference point, ie, the current first instruction.
So, PC always points to the third instruction,
Or PC always points to the currently executing instruction address plus 2 instructions address.
When the processor is in ARM state, each instruction is 4 bytes, so the PC is executing the instruction address plus 8 bytes, that is:
PC = current position + 8 bytes execution
When the processor is in the Thumb state, each instruction is 2 bytes, 4 bytes of the instruction address plus PC is being executed, that is:
PC = current position + 4 bytes of program execution
The following example of a very good description of the problem.
- 0x4000 ADDPC, PC, # 4; instruction being executed, the write address value PC PC + 4
- 0x4004 ...; instruction being decoded
- 0x4008 ...; being fetched instruction, PC = 0x4008
- 0x400C ...;PC+4=0x400C
Further Supplementary Note that the above description, only the full performance of the pipeline is filled when the instruction to complete execution per clock cycle (single cycle instruction only) of an instruction.
If the program jump occurs, the pipeline is cleared, it will take a few clock to make the pipeline is filled again. Thus, possible to use less jump instructions can improve the efficiency of program
Representative of the program counter PC, the use of three pipeline stages, so the instruction is divided into three phases: 1 Fetch (loading instruction from a memory); second decoding (identifying the instruction to be executed); 3 performed (processing. instruction and writes the result back to the register). And R15 (PC) always points "are fetch" command, rather than to command "being executed" or being "decode" command. In general, people habitually agreed to "instruction is being executed as a reference point", called the current first instruction, so the PC always points to the third instruction. When the ARM state, each instruction is 4 bytes long, so the PC always points to the address of the instruction address plus 8 bytes, namely: PC = current program execution to +8;
ARM instructions are three lines, fetched translation means, while performing when executed, PC now points to the fetch address is then translated means being cpu instruction address is PC-4 (assuming the ARM state, a instruction 4 bytes), address of the instruction being executed cpu is PC-8, PC that is pointed to by the address and instruction addresses are now performed by a difference of 8.
When the interrupt occurs suddenly, is the preservation of the PC address
So you know, if returned when the return PC, then there is an intermediate instruction is not executed, so use SUB pc lr-irq # 4.
Article Source: http: //blog.csdn.net/enlaihe/article/details/7598941